Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4169
-gerrit
commit 78cd50e2ab25bee66bf8b179a4b0649db730702b Author: Duncan Laurie dlaurie@chromium.org Date: Tue May 14 11:16:34 2013 -0700
slippy: Minor vboot related fixes
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data
Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/google/slippy/acpi_tables.c | 6 ++++-- src/mainboard/google/slippy/chromeos.c | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 22 +++++++++++++++++++--- src/southbridge/intel/lynxpoint/lpc.c | 20 +------------------- src/vendorcode/google/chromeos/gnvs.c | 8 +++++++- 6 files changed, 32 insertions(+), 27 deletions(-)
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index a53ac00..a2ef673 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index e08a7ce..9c179e8 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -31,6 +31,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h>
extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -99,8 +100,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) #if CONFIG_CHROMEOS // TODO(reinauer) this could move elsewhere? chromeos_init_vboot(&(gnvs->chromeos)); - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif
/* Update the mem console pointer. */ diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 51d625b..1b70fde 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* The dev-switch is virtual */ int get_developer_mode_switch(void) { - return 0; + return 1; }
/* There are actually two recovery switches. One is the magic keyboard chord, diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 7a24e1f..38506c9 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,10 +20,12 @@
#include <console/console.h> #include <arch/io.h> +#include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> #include <elog.h> #include "pch.h" +#include "chip.h"
#if CONFIG_INTEL_LYNXPOINT_LP #include "lp_gpio.h" @@ -96,15 +98,29 @@ static int sleep_type_s3(void)
static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct southbridge_intel_lynxpoint_config *config = NULL;
/* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); }
int early_pch_init(const void *gpio_map, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c3b5322..33d74f1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -520,18 +520,6 @@ static void pch_fixups(struct device *dev) RCBA32_OR(0x21a8, 0x3); }
-static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -712,12 +700,6 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); }
-static void pch_lpc_enable_resources(device_t dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(device_t dev) { /* Enable PCH Display Port */ @@ -745,7 +727,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 5ee3665..ba1588d 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -49,9 +49,15 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos)
vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
- if (vboot_handoff != NULL) + if (vboot_handoff != NULL) { + vboot_handoff->init_params.flags |= VB_INIT_FLAG_OPROM_MATTERS; + if (oprom_is_loaded) + vboot_handoff->init_params.flags |= + VB_INIT_FLAG_OPROM_LOADED; + memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], ARRAY_SIZE(chromeos->vdat)); + } #endif
#if CONFIG_ELOG