Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )
Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ......................................................................
Patch Set 66:
(15 comments)
https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/su... File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md:
https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/su... PS64, Line 31: 0x235=03 and 0x13E=84
o. […]
I don't know. Probably fTPM
https://review.coreboot.org/c/coreboot/+/37441/64/Documentation/mainboard/su... PS64, Line 41: Coffe
Coffee
Ack
https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... PS64, Line 3:
lockdown missing
This should be a Kconfig setting.
https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... PS64, Line 10: device pci 01.0 on end
missing comment
Ack
https://review.coreboot.org/c/coreboot/+/37441/64/src/mainboard/supermicro/x... PS64, Line 16: device pci 14.2 on end
missing comment
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 10: device pci 01.0 on end
Missing comment.
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 16: device pci 14.2 on end
Missing comment.
I've no idea of what this is
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 19: device pci 16.0 on end # Management Engine Interface
Add interface number
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 20: device pci 16.1 on end # Management Engine Interface
Same
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 21: device pci 16.4 on end # Management Engine Interface
Same
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 23: device pci 1c.1 on
Missing comment.
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 20: register "PchHdaDspEnable" = "0"
drop disabled options
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" :
drop the ones for disabled ports
Looks like the clksrc/clkreq mapping isn't linear.
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 110: : # Disable S0ix : register "s0ix_enable" = "0" :
drop disabled functions
Ack
https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/x... PS65, Line 114: device domain 0 on
Please add root port numbers.
Ack