[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding

[Michał Żygowski (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63461

to look at the new patch set (#3).

Change subject: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
......................................................................

soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding

Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.

Signed-off-by: Michał Żygowski 
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
---
M src/soc/intel/alderlake/bootblock/pch.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/63461/3