Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57069 )
Change subject: coreboot tables: Add tcss information to coreboot table ......................................................................
coreboot tables: Add tcss information to coreboot table
This change adds tcss information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and HSL orientation for the board.
BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds correctly (volteer has CONFIG_SOC_INTEL_COMMON_BLOCK_TCSS set), and TEST='emerge-brya coreboot chromeos-bootimage' and verify it builds correctly (brya does NOT have CONFIG_SOC_INTEL_COMMON_BLOCK_TCSS set)
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 5 files changed, 113 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/1
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 91f8486..9e4deb4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -82,6 +82,7 @@ CB_TAG_SMMSTOREV2 = 0x0039, CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_ACPI_CNVS = 0x0041, + CB_TAG_TCSS_INFO = 0x0042, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -142,6 +143,16 @@ u8 strings[0]; };
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +struct cb_tcss_info { + u32 tag; + u32 size; + /* port_count holds number of type-c ports supported by device */ + u32 port_count; + struct tcss_config_info tcss_info[MAX_TYPE_C_PORTS]; +}; +#endif + struct cb_string { u32 tag; u32 size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 26dece7..0892fba 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -148,6 +148,16 @@ #if CONFIG(LP_PCI) struct pci_access pacc; #endif + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + /* USB Type-C Port Configuration Info */ + struct { + uint8_t sbu_orientation; + uint8_t hsl_orientation; + uint8_t usb2_port_number; + uint8_t usb3_port_number; + } tcss_config_info[MAX_TYPE_C_PORTS]; +#endif };
extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 269275d..4436f8b 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -246,6 +246,18 @@ info->fmap_cache = get_cbmem_addr(ptr); }
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +static void cb_parse_tcss_info(void *ptr, struct sysinfo_t *info) +{ + int i; + const struct cb_tcss_info *tcss_entry = (struct cb_tcss *)ptr; + const struct tcss_config_info *tcss_info = tcss_entry->tcss_config_info; + + for (i = 0; i < tcss_entry->port_count; i++) + info->tcss_config_info[i] = tcss_info[i]; +} +#endif + #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -420,6 +432,11 @@ case CB_TAG_FMAP: cb_parse_fmap_cache(ptr, info); break; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + case CB_TAG_TCSS_INFO: + cb_parse_tcss_info(ptr, info); + break; +#endif default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index fd7461d5..87979ea 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -3,6 +3,7 @@ #ifndef COMMONLIB_COREBOOT_TABLES_H #define COMMONLIB_COREBOOT_TABLES_H
+#include <intelblocks/tcss.h> #include <stdint.h>
/* The coreboot table information is for conveying information @@ -84,6 +85,7 @@ LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, + LB_TAG_TCSS_INFO = 0x0042, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -421,6 +423,27 @@ int32_t early_cmd1_status; };
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +/* + * USB TCSS Configuration Information + * This record contains board-specific TCSS configuration information. + * There will be one record per type-C port. + */ +struct tcss_config_info { + uint8_t usb2_port_number; + uint8_t usb3_port_number; + uint8_t sbu_orientation; + uint8_t hsl_orientation; +}; + +struct lb_tcss_info { + uint32_t tag; + uint32_t size; + uint32_t port_count; + struct tcss_config_info tcss_info[MAX_TYPE_C_PORTS]; +}; +#endif + struct lb_macs { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 27f5315..6cf6160 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cbconfig.h> +#include <assert.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -32,6 +33,10 @@ void lb_string_platform_blob_version(struct lb_header *header); #endif
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +int variant_get_tcss_sysinfo(struct tcss_config_info *info); +#endif + static struct lb_header *lb_table_init(unsigned long addr) { struct lb_header *header; @@ -233,6 +238,48 @@ rec->early_cmd1_status = *ms_cbmem; }
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +int __weak variant_get_tcss_sysinfo(struct tcss_config_info *info) +{ + /* Default weak implementation - return 0 ports supported */ + return 0; +} + +static void lb_add_tcss_info(struct lb_header *header) +{ + int count = 0; + int i; + struct lb_tcss_info *rec; + struct tcss_config_info variant_tcss_info[MAX_TYPE_C_PORTS]; + + count = variant_get_tcss_sysinfo(variant_tcss_info); + if (count == 0) + return; + + ASSERT(count <= MAX_TYPE_C_PORTS); + + rec = (struct lb_tcss_info *)lb_new_record(header); + if (!rec) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + return; + } + + rec->tag = LB_TAG_TCSS_INFO; + rec->size = sizeof(*rec); + rec->port_count = count; + for (i = 0; i < count; i++) { + rec->tcss_info[i] = variant_tcss_info[i]; + + printk(BIOS_INFO, "Passing conn%d tcss info to payload: " + "usb2:%d usb3:%d sbu:%d hsl:%d\n", i, + rec->tcss_info[i].usb2_port_number, + rec->tcss_info[i].usb3_port_number, + rec->tcss_info[i].sbu_orientation, + rec->tcss_info[i].hsl_orientation); + } +} +#endif /* CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) */ + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -522,6 +569,11 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head);
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + /* Add tcss information */ + lb_add_tcss_info(head); +#endif + /* Remember where my valid memory ranges are */ return lb_table_fini(head); }