yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46579 )
Change subject: WIP: coreboot: Add eDP edid to skip get edid fail ......................................................................
WIP: coreboot: Add eDP edid to skip get edid fail
Add eDP edid to skip get edid fail and start display development
Signed-off-by: Huijuan Xie huijuan.xie@mediatek.corp-partner.google.com Change-Id: I58c7ea1fd45a2def87593f9436d2c513c5b502af --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 3 files changed, 67 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46579/1
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9f0b2e1..eb7e661 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -828,6 +828,26 @@ return ret; }
+/*Add eDP EDID to skip get edid fail*/ +static const u8 edp_edid[128] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x0d, 0xae, 0x47, 0x12, 0x00, 0x00, 0x00, 0x00, + 0x13, 0x1c, 0x01, 0x04, 0x95, 0x19, 0x11, 0x78, + 0x02, 0x67, 0x75, 0x98, 0x59, 0x53, 0x90, 0x27, + 0x1c, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x61, 0x1f, + 0x56, 0x56, 0x50, 0x90, 0x0a, 0x30, 0x30, 0x20, + 0x36, 0x00, 0xfd, 0xa9, 0x00, 0x00, 0x00, 0x18, + 0x00, 0x00, 0x00, 0xfe, 0x00, 0x4e, 0x31, 0x32, + 0x30, 0x41, 0x43, 0x41, 0x2d, 0x45, 0x41, 0x31, + 0x0a, 0x20, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x43, + 0x4d, 0x4e, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfe, + 0x00, 0x4e, 0x31, 0x32, 0x30, 0x41, 0x43, 0x41, + 0x2d, 0x45, 0x41, 0x31, 0x0a, 0x20, 0x00, 0xea, +}; + int anx7625_dp_get_edid(uint8_t bus, struct edid *out) { int block_num; @@ -835,6 +855,9 @@ u8 edid[FOUR_BLOCK_SIZE];
block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + block_num=1; + + memcpy(edid, &edp_edid, sizeof(edp_edid)); if (block_num < 0) { ANXERROR("Failed to get eDP EDID.\n"); return -1; diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2505bbc..ac289c8 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -130,8 +130,11 @@ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) tmp_reg1 = SYNC_PULSE_MODE; } - +#if 1 //DSI pattern write32(&dsi0->dsi_mode_ctrl, tmp_reg1); + write32(&dsi0->dsi_bist_pattern, 0xff00); + write32(&dsi0->dsi_bist_con, 0x40); +#endif }
static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) @@ -415,7 +418,7 @@ { u32 data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); - + data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); if (!data_rate) return -1; @@ -434,5 +437,38 @@ mtk_dsi_set_mode(mode_flags); mtk_dsi_start();
+ printk(BIOS_ERR, "dsi_start = 0x%08x\n", read32(&dsi0->dsi_start)); + printk(BIOS_ERR, "dsi_inten = 0x%08x\n", read32(&dsi0->dsi_inten)); + printk(BIOS_ERR, "dsi_intsta = 0x%08x\n", read32(&dsi0->dsi_intsta)); + printk(BIOS_ERR, "dsi_con_ctrl = 0x%08x\n", read32(&dsi0->dsi_con_ctrl)); + printk(BIOS_ERR, "dsi_mode_ctrl = 0x%08x\n", read32(&dsi0->dsi_mode_ctrl)); + printk(BIOS_ERR, "dsi_txrx_ctrl = 0x%08x\n", read32(&dsi0->dsi_txrx_ctrl)); + printk(BIOS_ERR, "dsi_psctrl = 0x%08x\n", read32(&dsi0->dsi_psctrl)); + printk(BIOS_ERR, "dsi_vsa_nl = 0x%08x\n", read32(&dsi0->dsi_vsa_nl)); + printk(BIOS_ERR, "dsi_vbp_nl = 0x%08x\n", read32(&dsi0->dsi_vbp_nl)); + printk(BIOS_ERR, "dsi_vfp_nl = 0x%08x\n", read32(&dsi0->dsi_vfp_nl)); + printk(BIOS_ERR, "dsi_vact_nl = 0x%08x\n", read32(&dsi0->dsi_vact_nl)); + printk(BIOS_ERR, "dsi_lfr_con = 0x%08x\n", read32(&dsi0->dsi_lfr_con)); + printk(BIOS_ERR, "dsi_lfr_sta = 0x%08x\n", read32(&dsi0->dsi_lfr_sta)); + printk(BIOS_ERR, "dsi_size_con = 0x%08x\n", read32(&dsi0->dsi_size_con)); + printk(BIOS_ERR, "dsi_vfp_early_stop = 0x%08x\n", read32(&dsi0->dsi_vfp_early_stop)); + printk(BIOS_ERR, "dsi_hsa_wc = 0x%08x\n", read32(&dsi0->dsi_hsa_wc)); + printk(BIOS_ERR, "dsi_hbp_wc = 0x%08x\n", read32(&dsi0->dsi_hbp_wc)); + printk(BIOS_ERR, "dsi_hfp_wc = 0x%08x\n", read32(&dsi0->dsi_hfp_wc)); + printk(BIOS_ERR, "dsi_bllp_wc = 0x%08x\n", read32(&dsi0->dsi_bllp_wc)); + printk(BIOS_ERR, "dsi_cmdq_size = 0x%08x\n", read32(&dsi0->dsi_cmdq_size)); + printk(BIOS_ERR, "dsi_hstx_cklp_wc = 0x%08x\n", read32(&dsi0->dsi_hstx_cklp_wc)); + printk(BIOS_ERR, "dsi_phy_lccon = 0x%08x\n", read32(&dsi0->dsi_phy_lccon)); + printk(BIOS_ERR, "dsi_phy_ld0con = 0x%08x\n", read32(&dsi0->dsi_phy_ld0con)); + printk(BIOS_ERR, "dsi_phy_timecon0 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon0)); + printk(BIOS_ERR, "dsi_phy_timecon1 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon1)); + printk(BIOS_ERR, "dsi_phy_timecon2 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon2)); + printk(BIOS_ERR, "dsi_phy_timecon3 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon3)); + printk(BIOS_ERR, "dsi_vm_cmd_con = 0x%08x\n", read32(&dsi0->dsi_vm_cmd_con)); + printk(BIOS_ERR, "dsi_bist_pattern = 0x%08x\n", read32(&dsi0->dsi_bist_pattern)); + printk(BIOS_ERR, "dsi_bist_con = 0x%08x\n", read32(&dsi0->dsi_bist_con)); + printk(BIOS_ERR, "dsi_force_commit = 0x%08x\n", read32(&dsi0->dsi_force_commit)); + return 0; } + diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7bacec1..edb597a 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -75,10 +75,13 @@ u32 dsi_phy_timecon2; u32 dsi_phy_timecon3; u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[92]; + u32 dsi_vm_cmd_con;/*0x130*/ + u8 reserved5[68]; + u32 dsi_bist_pattern; /*0x178*/ + u32 dsi_bist_con;/* 0x17c */ + u8 reserved6[16]; u32 dsi_force_commit; /* Available since MT8183 */ - u8 reserved6[108]; + u8 reserved7[108]; u32 dsi_cmdq[128]; }; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;