Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68897 )
Change subject: cpu/x86/smm: Move setting up 64bit mode earlier ......................................................................
cpu/x86/smm: Move setting up 64bit mode earlier
Now there is no need to do it that late in the smm stub. Since we don't need the stack to save EFER MSR anymore.
This also removes the need exit back to protected mode for the fxrstor instruction. A further advantage is that all XMM regs (remember that there are more in long mode) are now properly saved.
Change-Id: Ie247d6fba0dbc953a810038465f1e0d42ca171cf Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/smm/smm_stub.S 1 file changed, 21 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/68897/1
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f34eeaf..550d498 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -136,6 +136,10 @@ movw %ax, %fs movw %ax, %gs /* Used by cpu_info in ramstage */
+#if ENV_X86_64 +#include <cpu/x86/64bit/entry64.inc> +#endif + /* The CPU number is calculated by reading the initial APIC id. Since * the OS can manipulate the APIC id use the non-changing cpuid result * for APIC id (eax). A table is used to handle a discontiguous @@ -231,12 +235,6 @@ * c_handler(&arg) */ #if ENV_X86_64 - mov %ecx, %edi - /* entry64.inc preserves ebx, esi, edi, ebp */ -#include <cpu/x86/64bit/entry64.inc> - mov %edi, %ecx - - push %rbx /* uintptr_t *canary */ push %rcx /* size_t cpu */
@@ -244,14 +242,6 @@
movabs c_handler, %eax call *%rax - - /* - * The only reason to go back to protected mode is because we called fxsave - * protected mode. - */ - - /* Disable long mode. */ - #include <cpu/x86/64bit/exit32.inc> #else push $0x0 /* Padding */ push %ebx /* uintptr_t *canary */