Andrey Petrov (andrey.petrov@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17234
-gerrit
commit 35a856e656ca300db0e0a2411b129d891c640900 Author: Andrey Petrov andrey.petrov@intel.com Date: Fri Nov 4 15:37:27 2016 -0700
WIP: soc/intel/common: Enable SPI NVM functions in pre-ram stages
Put global variable into car global.
BUG=chrome-os-partner:57515 CQ-DEPEND=CL:*303016 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle.
Change-Id: I35ea29096abcdde482b99d90db022b7c7bc95c29 Signed-off-by: Andrey Petrov andrey.petrov@intel.com --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nvm.c | 22 +++++++++++++++++----- 2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..51b6f86 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 6b86faf..e4d8bbd 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <arch/early_variables.h> #include <stdint.h> #include <stddef.h> #include <bootmode.h> @@ -28,16 +29,17 @@ * address space for reading. Also this module assumes an area it erased * when all bytes read as all 0xff's. */
-static struct spi_flash *flash; +static struct spi_flash *gflash CAR_GLOBAL;
static int nvm_init(void) { - if (flash != NULL) - return 0; + struct spi_flash **flash_ptr = car_get_var_ptr(&gflash);
+ if (*flash_ptr != NULL) + return 0; spi_init(); - flash = spi_flash_probe(0, 0); - if (!flash) { + *flash_ptr = spi_flash_probe(0, 0); + if (!*flash_ptr) { printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; } @@ -79,25 +81,35 @@ int nvm_is_erased(const void *start, size_t size)
int nvm_erase(void *start, size_t size) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1; + flash = (struct spi_flash*) car_get_var(gflash); return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); }
/* Write data to NVM. Returns 0 on success < 0 on error. */ int nvm_write(void *start, const void *data, size_t size) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1; + flash = car_get_var(gflash); return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); }
/* Read flash status register to determine if write protect is active */ int nvm_is_write_protected(void) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1;
+ flash = car_get_var(gflash); + if (IS_ENABLED(CONFIG_CHROMEOS)) { u8 sr1; u8 wp_gpio;