[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell: Use IRQ 9 for SCI

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31785 )

Change subject: soc/intel/braswell: Use IRQ 9 for SCI
......................................................................

soc/intel/braswell: Use IRQ 9 for SCI

Default reserved value of used for SCI IRQ.
Configure SCIS field to use IRQ 9.

BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux

Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0
Signed-off-by: Frans Hendriks 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785
Tested-by: build bot (Jenkins) 
Reviewed-by: Michał Żygowski 
---
M src/soc/intel/braswell/southcluster.c
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Michał Żygowski: Looks good to me, approved

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index b8263db..e79cb12 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008-2009 coresystems GmbH
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
- * Copyright (C) 2018 Eltan B.V.
+ * Copyright (C) 2018-2019 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -267,6 +267,7 @@
    int i;
    const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
    const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
+	const unsigned long ilb_base = ILB_BASE_ADDRESS;
    void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1);
    const struct soc_irq_route *ir = &global_soc_irq_route;
    struct soc_intel_braswell_config *config = dev->chip_info;
@@ -274,6 +275,14 @@
    printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));

+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND,
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+		PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+
+	/* Use IRQ9 for SCI Interrupt */
+	write32((void *)(ilb_base + ACTL), 0);
+
    isa_dma_init();

/* Set up the PIRQ PIC routing based on static config. */