[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: Fix GPIO table for v3.6 schematics for woomax

[Aaron Durbin (Code Review)]

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44655 )

Change subject: mb/google/zork: Fix GPIO table for v3.6 schematics for woomax
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mb/google/zork: Fix GPIO table for v3.6 schematics for woomax

Add board version switch GPIO table on gpio.c.

BUG=b:165887084
BRANCH=Zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen 
Change-Id: I661e16f7b4769e83450f41ff267c0d253441c4cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44655
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/zork/variants/woomax/gpio.c
1 file changed, 36 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c
index 968c622..ebbcbea 100644
--- a/src/mainboard/google/zork/variants/woomax/gpio.c
+++ b/src/mainboard/google/zork/variants/woomax/gpio.c
@@ -3,7 +3,7 @@
 #include <baseboard/variants.h>
 #include <soc/gpio.h>

-static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = {
+static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = {
    /* GPIO_4 NC */
    PAD_NC(GPIO_4),
    /* GPIO_5 NC */
@@ -30,8 +30,43 @@
    PAD_NC(GPIO_143),
 };

+static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = {
+	/* GPIO_4 NC */
+	PAD_NC(GPIO_4),
+	/* GPIO_5 NC */
+	PAD_NC(GPIO_5),
+	/* GPIO_6 NC */
+	PAD_NC(GPIO_6),
+	/* GPIO_11 NC */
+	PAD_NC(GPIO_11),
+	/* GPIO_32 NC */
+	PAD_NC(GPIO_32),
+	/* GPIO_69 NC */
+	PAD_NC(GPIO_69),
+	/* RAM_ID_4  */
+	PAD_NC(GPIO_84),
+	/* EN_DEV_BEEP_L */
+	PAD_GPO(GPIO_89, HIGH),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
+	/* GPIO_141 NC */
+	PAD_NC(GPIO_141),
+	/* GPIO_143 NC */
+	PAD_NC(GPIO_143),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
+	uint32_t board_version;
+
+	/* If board version cannot be read, assume it is board_version 0. */
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 0;
+
+	if (board_version == 0) {
+		*size = ARRAY_SIZE(woomax_bid0_gpio_set_stage_ram);
+		return woomax_bid0_gpio_set_stage_ram;
+	}
    *size = ARRAY_SIZE(woomax_gpio_set_stage_ram);
    return woomax_gpio_set_stage_ram;
 }