Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )
Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
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Patch Set 2:
Patch Set 2:
What difference does it make?
Well, first of all it sets the SI bit of the RP PCI device. That can
influence any software acting on that bit. I just read a comment that
it also enables the PDS (present detect state?) otherwise it might be
stuck at 1, idk. IIRC, FSP runs a timeout for all RPs that implement
a slot at once to detect presence of downstream devices. There maybe
more that I don't recall atm or just don't know ;)
Thanks for clearing this up for me :)
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