Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61680 )
Change subject: soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region ......................................................................
soc/amd/common/block/pci/amd_pci_mmconf: add assert for MMCONF region
Add an assert that CONFIG_ECAM_MMCONF_BASE_ADDRESS only has bits set in the lower 32 bits. The current code assumes that it doesn't have any higher bits set and that it will always be below the 4GB boundary. This is not a hardware limitation.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ib0b4443d7a86f20c4c2508a88db5d731560f8312 --- M src/soc/amd/common/block/pci/amd_pci_mmconf.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61680/1
diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index fb4db39..0296199 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/amd_pci_mmconf.h> +#include <assert.h> #include <cpu/amd/msr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -9,6 +10,10 @@ { msr_t mmconf;
+ /* The hardware supports having the PCI MMCONF base address above 4GB, but 32 bit + coreboot doesn't. */ + _Static_assert(((uint64_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS >> 32) == 0, + "PCI MMCONF base is above 4GB."); mmconf.hi = 0; mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN | fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;