[coreboot-gerrit] Change in coreboot[master]: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44891 )

Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
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mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree

BUG=b:149970243
BRANCH=zork

Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546
Signed-off-by: Felix Held 
---
M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
2 files changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44891/1

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 5a86b1c..140b775 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -180,6 +180,15 @@

register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

+	# genral purpose PCIe clock output configuration
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
+	register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[4]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[5]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
    device cpu_cluster 0 on
    	device lapic 0 on end
    end
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index 4be866d..d67c554 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -26,7 +26,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ2,
    },
    {
    	// WLAN
@@ -40,7 +39,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0,
    },
    {
    	// SD Reader
@@ -54,7 +52,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1,
    }
 };