Hello build bot (Jenkins), Raul Rangel, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41247
to look at the new patch set (#4).
Change subject: soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions ......................................................................
soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions
This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM
This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 30 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/41247/4