[coreboot-gerrit] [S] Change in coreboot[master]: src/soc/intel: Add in-code documentation

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71664 )

Change subject: src/soc/intel: Add in-code documentation
......................................................................

src/soc/intel: Add in-code documentation

Signed-off-by: Maximilian Brune 
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/common/block/include/intelblocks/meminit.h
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
3 files changed, 15 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/71664/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 82493a7..8deeb96 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -152,8 +152,8 @@
 };

enum ddi_port_flags {
-	DDI_ENABLE_DDC = 1 << 0,
-	DDI_ENABLE_HPD = 1 << 1,
+	DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
+	DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
 };

/*
diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h
index 3ebf536..a4fb9fa 100644
--- a/src/soc/intel/common/block/include/intelblocks/meminit.h
+++ b/src/soc/intel/common/block/include/intelblocks/meminit.h
@@ -22,8 +22,8 @@

/* Different memory topologies supported by the platform. */
 enum mem_topology {
-	MEM_TOPO_MEMORY_DOWN = BIT(0),
-	MEM_TOPO_DIMM_MODULE = BIT(1),
+	MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board
+	MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules
    MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE,
 };

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index a4e3500..be7c5f9 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -15,6 +15,7 @@

enum pcie_rp_flags {
    PCIE_RP_HOTPLUG = (1 << 0),
+	/* PCIE RP Latency Tolerance Report */
    PCIE_RP_LTR = (1 << 1),
    /* PCIE RP Advanced Error Report */
    PCIE_RP_AER = (1 << 2),