[coreboot-gerrit] Change in coreboot[master]: vendorcode/google/chromeos: Introduce helper for CSE board reset

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44646 )

Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset
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vendorcode/google/chromeos: Introduce helper for CSE board reset

When CSE Lite jumps from RO to RW, certain boards need to request
Embedded Controller (EC) to trigger cold reset of SoC. This change
introduces a helper to override the default global reset.

BUG=None
TEST=Build and boot the drawcia to OS.

Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/vendorcode/google/chromeos/Kconfig
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/cse_board_reset.c
3 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/1

diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index f48069f..4dc6000 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -92,5 +92,14 @@
      to ACPI DSD table in device driver. These parameters will be applied by kernel driver
      through device property at boot.

+config CHROMEOS_CSE_BOARD_RESET_OVERRIDE
+	bool
+	default n
+	depends on SOC_INTEL_CSE_LITE_SKU
+	help
+	  On some boards that run old firmware version in cr50, Embedded Controller (EC) needs
+	  to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW.
+	  Enabling this config will help to override the default global reset.
+
 endif # CHROMEOS
 endmenu
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index a25700f..fd9398e 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -10,6 +10,7 @@
 ramstage-$(CONFIG_USE_SAR) += sar.c
 ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c
 ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c
+ramstage-$(CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c

bootblock-y += watchdog.c
 verstage-y += watchdog.c
diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c
new file mode 100644
index 0000000..0768e6d
--- /dev/null
+++ b/src/vendorcode/google/chromeos/cse_board_reset.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/cache.h>
+#include <arch/io.h>
+#include <cf9_reset.h>
+#include <ec/google/chromeec/ec.h>
+#include <halt.h>
+#include <intelblocks/cse.h>
+
+void cse_board_reset(void)
+{
+	/* TODO: Check tpm firmware version before initiating AP reset. */
+	dcache_clean_all();
+	outb(FULL_RST | SYS_RST, RST_CNT);
+	if (!google_chromeec_ap_reset())
+		halt();
+}
+