Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11029
-gerrit
commit fb2f0c0fa2c1a8cb5194ce0cfce2cd63a025eab3 Author: Aaron Durbin adurbin@chromium.org Date: Mon Jul 20 14:28:01 2015 -0500
skylake: provide more clarity for PCR access
The current primary to sideband (P2SB) code for private configuration register (PCR) access weren't very clear with the naming or reasoning for some of the code. Provide more verbiage surrounding this interface.
BUG=None BRANCH=None TEST=Built and booted glados.
Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247 Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/286900 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/skylake/include/soc/pcr.h | 5 ++++- src/soc/intel/skylake/pcr.c | 16 +++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 9ac9edd..a6987cb 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -16,9 +16,12 @@ #ifndef _SOC_PCR_H_ #define _SOC_PCR_H_
+/* + * Primary to sideband (P2SB) for private configuration registers (PCR). + */ + /* PCH (SunRisePoint LP) */ #define PCH_PCR_BASE_ADDRESS 0xFD000000 -#define R_PCH_PCR_LPC_GCFD 0x3418
/* DMI Control Register */ #define R_PCH_PCR_DMI_DMIC 0x2234 diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 33d6cd1..79c32f9 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -70,6 +70,19 @@ u8 pcr_read8(PCH_SBI_PID pid, u16 offset, u8 *outdata) }
/* + * After every write one needs to perform a read an innocuous register to + * ensure the writes are completed for certain ports. This is done for + * all ports so that the callers don't need the per-port knowledge for + * each transaction. + */ +static inline void complete_write(void) +{ + /* Read the general control and function disable register. */ + const size_t R_PCH_PCR_LPC_GCFD = 0x3418; + read32(PCH_PCR_ADDRESS(PID_LPC, R_PCH_PCR_LPC_GCFD)); +} + +/* * Write PCR register. (This is internal function) * It returns PCR register and size in 1/2/4 bytes. * The offset should not exceed 0xFFFF and must be aligned with size @@ -101,7 +114,8 @@ static u8 pch_pcr_write(PCH_SBI_PID pid, u16 offset, u32 size, u32 data) default: break; } - read32(PCH_PCR_ADDRESS(PID_LPC, R_PCH_PCR_LPC_GCFD)); + /* Ensure the writes complete. */ + complete_write();
return 0; }