[coreboot-gerrit] [S] Change in coreboot[master]: [WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_de...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74440 )

Change subject: [WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_device()
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[WIP] asus/p2b, emulation/qemu-i440fx: Use acpigen_write_processor_device()

FADT P_LVLx had values that disabled C2/C3 state transitions.

Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775
Signed-off-by: Kyösti Mälkki 
---
M src/southbridge/intel/i82371eb/acpi_tables.c
M src/southbridge/intel/i82371eb/fadt.c
2 files changed, 17 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74440/1

diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 15f2c429..17ff2ab 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -6,13 +6,13 @@
 #include <device/device.h>
 #include "i82371eb.h"

-
 static void generate_cpu_entry(int cpu)
 {
-	int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6;
+	acpigen_write_processor_device(cpu);

-	acpigen_write_processor(cpu, pcontrol_blk, plen);
-	acpigen_pop_len();
+	/* TBD: _PTC to communicate clock throttling */
+
+	acpigen_write_processor_device_end();
 }

void generate_cpu_entries(const struct device *device)
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 681d09c..5122dcf 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -38,6 +38,7 @@

fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
    fadt->duty_width = 3; /* this width is in bits */
+
    fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
    fadt->mon_alrm = 0x0; /* not supported */
    /*