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https://review.coreboot.org/c/coreboot/+/61937
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Change subject: soc/intel/adl: Select Kconfig to correct TBT port number ......................................................................
soc/intel/adl: Select Kconfig to correct TBT port number
Select Kconfig to enable TBT root port index correction code in coreboot. In Alderlake, TBT PCIe root port LCAP registers return index starting from 2 and coreboot needs to correct index to align with index 0.
Selecting Kconfig will allow common code to return correct 0 based index.
Also, added support function which returns whether the slot is TBT PCIe or not.
BUG=b:210933428 BRANCH=None TEST=Check TBT PCIe remap happens correctly on Brya board.
Change-Id: I9c2bd43d7c9ba570fcec8e71a244840160ba81ff Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/pcie_rp.c 2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/61937/3