Jérémy Compostella has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )
Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+ ......................................................................
soc/intel/common/block/cpu: Use the effective way size for NEM+
The Last Level Cache (LLC) way size (or sets) is not necessarily a power of two. However, on some platforms, the effective way size, the way size which should be considered for No-Eviction Mode (NEM) purposes is the biggest power of two of the way size.
Alder Lake External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides some understanding that the maximum NEM size depends on the number of CBO which used to be accessible via MSR 0x396. Unfortunately, this MSR is not available and as a general implementation the recommendation is to use the biggest power of two of the way size instead.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduce to control this behavior.
BUG=b:360332771 TEST=Verified on rex
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83946/2