[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

[Shuo Liu (Code Review)]

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, [e-mail].

Shuo Liu has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )

Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 17:

(7 comments)

File src/soc/intel/snowridge/Kconfig:

https://review.coreboot.org/c/coreboot/+/83321/comment/70467ac5_0d6f6afc?usp... :
PS15, Line 42: 	select FSP_T_XIP
> Should FSP_S_XIP be selected as well?

Close this, in this SoC, FSP_S is put at fixed location in flash but still relocatable.

File src/soc/intel/snowridge/chip.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/b168d107_dfa82a4b?usp... :
PS15, Line 418: 	}
will the common pci codes do this again?

File src/soc/intel/snowridge/sriov.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/0fde3d77_e8cfcf8d?usp... :
PS15, Line 13: void pciexp_vf_read_resources(struct device *dev)
if coreboot only enables PF, can the OS still work?

https://review.coreboot.org/c/coreboot/+/83321/comment/02c19b57_df091187?usp... :
PS15, Line 76: 			resource->flags |= IORESOURCE_ABOVE_4G;
is this VF req or RCiEP req?

File src/soc/intel/snowridge/systemagent.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/0ee754a8_75ee264e?usp... :
PS15, Line 17: 	*size = CONFIG_ECAM_MMCONF_LENGTH;
> Shouldn't be probed by BAR access?

CONFIG_ECAM_MMCONF_LENGTH => should be aligned with the probed value

https://review.coreboot.org/c/coreboot/+/83321/comment/e15ee06b_b0f80e9d?usp... :
PS15, Line 32: void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt)
resource_cnt -> resource_index?

https://review.coreboot.org/c/coreboot/+/83321/comment/538fb3df_1f550413?usp... :
PS15, Line 56: I
PCIe MMCFG BAR?