Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83862?usp=email )
Change subject: soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devices ......................................................................
soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devices
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2].
[1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44
Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/83862/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8ff52a6..dbb90d7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4184,12 +4184,8 @@ #define PCI_DID_INTEL_CML_GT2_ULX_1 0x9B40 #define PCI_DID_INTEL_CML_GT1_S_1 0x9BA5 #define PCI_DID_INTEL_CML_GT1_S_2 0x9BA8 -#define PCI_DID_INTEL_CML_GT2_S_1 0x9B45 -#define PCI_DID_INTEL_CML_GT2_S_2 0x9B48 #define PCI_DID_INTEL_CML_GT1_H_1 0x9BA4 #define PCI_DID_INTEL_CML_GT1_H_2 0x9BA2 -#define PCI_DID_INTEL_CML_GT2_H_1 0x9B44 -#define PCI_DID_INTEL_CML_GT2_H_2 0x9B42 #define PCI_DID_INTEL_CML_GT2_S_G0 0x9BC8 #define PCI_DID_INTEL_CML_GT2_S_P0 0x9BC5 #define PCI_DID_INTEL_CML_GT2_H_R0 0x9BC2 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index c062746..de6b064 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -146,14 +146,10 @@ { PCI_DID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }, { PCI_DID_INTEL_CML_GT1_S_1, "CometLake S GT1" }, { PCI_DID_INTEL_CML_GT1_S_2, "CometLake S GT1" }, - { PCI_DID_INTEL_CML_GT2_S_1, "CometLake S GT2" }, - { PCI_DID_INTEL_CML_GT2_S_2, "CometLake S GT2" }, { PCI_DID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" }, { PCI_DID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" }, { PCI_DID_INTEL_CML_GT1_H_1, "CometLake H GT1" }, { PCI_DID_INTEL_CML_GT1_H_2, "CometLake H GT1" }, - { PCI_DID_INTEL_CML_GT2_H_1, "CometLake H GT2" }, - { PCI_DID_INTEL_CML_GT2_H_2, "CometLake H GT2" }, { PCI_DID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" }, { PCI_DID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f1e7d7e..6b0abc9 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -403,12 +403,8 @@ PCI_DID_INTEL_CML_GT2_ULX_1, PCI_DID_INTEL_CML_GT1_S_1, PCI_DID_INTEL_CML_GT1_S_2, - PCI_DID_INTEL_CML_GT2_S_1, - PCI_DID_INTEL_CML_GT2_S_2, PCI_DID_INTEL_CML_GT1_H_1, PCI_DID_INTEL_CML_GT1_H_2, - PCI_DID_INTEL_CML_GT2_H_1, - PCI_DID_INTEL_CML_GT2_H_2, PCI_DID_INTEL_CML_GT2_S_G0, PCI_DID_INTEL_CML_GT2_S_P0, PCI_DID_INTEL_CML_GT2_H_R0,