Rishika Raj has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83555?usp=email )
Change subject: mb/google/brya/variants/orisa: Remove dummy USB2 Port 10 entry ......................................................................
mb/google/brya/variants/orisa: Remove dummy USB2 Port 10 entry
This removes the dummy entry for usb2_ports[9] as it doesn't exist on the SoC as per USB2 port mapping.
BUG=None TEST=emerge-nissa coreboot
Change-Id: I355e4cdf70fbbc049d92265b0dee62e1d1545e36 Signed-off-by: Rishika Raj rishikaraj@google.com --- M src/mainboard/google/brya/variants/orisa/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83555/1
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index f04eee2..9843272 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -90,7 +90,6 @@ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1