[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/glinda: Update SCI mapping

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84381?usp=email )

Change subject: soc/amd/glinda: Update SCI mapping
......................................................................

soc/amd/glinda: Update SCI mapping

source: PPR #57254 Rev 1.71

Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b
Signed-off-by: Maximilian Brune 
---
M src/soc/amd/glinda/include/soc/pci_devs.h
M src/soc/amd/glinda/xhci.c
2 files changed, 24 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/84381/1

diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h
index a37d3ee..0ef6864 100644
--- a/src/soc/amd/glinda/include/soc/pci_devs.h
+++ b/src/soc/amd/glinda/include/soc/pci_devs.h
@@ -66,7 +66,7 @@
 #define   GFX_HDA_DEVFN		PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC)

#define   XHCI0_DEV		0x0
-#define   XHCI0_FUNC		3
+#define   XHCI0_FUNC		0
 #define   XHCI0_DEVFN		PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)

#define   XHCI1_DEV		0x0
@@ -89,9 +89,14 @@
 #define PCIE_ABC_C_DEVFN	PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
 #define SOC_PCIE_GPP_C_DEV	_SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)

-#define   XHCI2_DEV		0x0
-#define   XHCI2_FUNC		0
-#define   XHCI2_DEVFN		PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
+#define   USB4_XHCI0_DEV	0x0
+#define   USB4_XHCI0_FUNC	3
+#define   USB4_XHCI0_DEVFN	PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC)
+
+#define   USB4_XHCI1_DEV	0x0
+#define   USB4_XHCI1_FUNC	4
+#define   USB4_XHCI1_DEVFN	PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC)
+

/* SMBUS */
 #define SMBUS_DEV		0x14
diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c
index 74e8816..70a0d84 100644
--- a/src/soc/amd/glinda/xhci.c
+++ b/src/soc/amd/glinda/xhci.c
@@ -25,7 +25,13 @@
    	.level = SMI_SCI_EDG
    },
    {
-		.scimap = SMITYPE_XHC2_PME,
+		.scimap = SMITYPE_XHC3_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC4_PME,
    	.gpe = GEVENT_31,
    	.direction = SMI_SCI_LVL_HIGH,
    	.level = SMI_SCI_EDG
@@ -41,18 +47,20 @@
    	return CB_ERR_ARG;

if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
-		if (dev->path.pci.devfn == XHCI0_DEVFN) {
-			*gpe = xhci_sci_sources[0].gpe;
-			return CB_SUCCESS;
-		} else if (dev->path.pci.devfn == XHCI1_DEVFN) {
+		if (dev->path.pci.devfn == XHCI1_DEVFN) {
    		*gpe = xhci_sci_sources[1].gpe;
    		return CB_SUCCESS;
    	}
    } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
-		if (dev->path.pci.devfn == XHCI2_DEVFN
-		    && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
+		if (dev->path.pci.devfn == XHCI0_DEVFN) {
+			*gpe = xhci_sci_sources[0].gpe;
+			return CB_SUCCESS;
+		} else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) {
    		*gpe = xhci_sci_sources[2].gpe;
    		return CB_SUCCESS;
+		} else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) {
+			*gpe = xhci_sci_sources[3].gpe;
+			return CB_SUCCESS;
    	}
    }