[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Fix board specific CSE reset

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44645 )

Change subject: mb/google/dedede: Fix board specific CSE reset
......................................................................

mb/google/dedede: Fix board specific CSE reset

As per the EDS, toggling SYS_RESET pin alone leads to warm reset. Set the
full reset bit in reset register before requesting EC to toggle SYS_RESET.
This will ensure that the cold reset is performed when CSE Lite jumps
from RO to RW.

BUG=b:162386991
TEST=Ensure that the cold reset is performed when CSE Lite jumps from RO
to RW. Please refer below the logs from Embedded Controller on receiving
the command to perform AP reset.
20-08-20 14:07:56.198 [14.593092 HC 0x125]
20-08-20 14:07:56.198 [14.593833 chipset_reset: 4]
20-08-20 14:07:56.230 [14.626565 power state 3 = S0, in 0x0039]
20-08-20 14:07:56.233 [14.627477 power state 8 = S0->S3, in 0x0039]
20-08-20 14:07:56.247 [14.643495 PD:S0->S3]
20-08-20 14:07:56.247 [14.644106 power state 2 = S3, in 0x0039]
20-08-20 14:07:56.254 [14.645666 power state 9 = S3->S5, in 0x0039]
20-08-20 14:07:56.278 [14.675107 PD:S3->S5]
20-08-20 14:07:56.279 [14.676098 VB hook_shutdown]
20-08-20 14:07:56.282 [14.676559 power state 1 = S5, in 0x0039]
20-08-20 14:07:57.310 [15.719640 power state 1 = S5, in 0x003f]
20-08-20 14:07:57.314 [15.720594 power state 6 = S5->S3, in 0x003f]
20-08-20 14:07:57.325 [15.735030 PD:S5->S3]
20-08-20 14:07:57.325 [15.735699 power state 2 = S3, in 0x003f]
20-08-20 14:07:57.332 [15.737500 power state 7 = S3->S0, in 0x003f]
20-08-20 14:07:57.346 [15.756216 PD:S3->S0]
20-08-20 14:07:57.347 [15.756650 power state 3 = S0, in 0x003f]

Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/mainboard/google/dedede/mainboard.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44645/1

diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
index 4695a9f..2725492 100644
--- a/src/mainboard/google/dedede/mainboard.c
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

#include <acpi/acpi.h>
+#include <arch/io.h>
 #include <bootstate.h>
 #include <baseboard/variants.h>
+#include <cf9_reset.h>
 #include <device/device.h>
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
@@ -13,6 +15,7 @@
 void cse_board_reset(void)
 {
    /* TODO: Check tpm firmware version before initiating AP reset. */
+	outb(FULL_RST | SYS_RST, RST_CNT);
    if (!google_chromeec_ap_reset())
    	halt();
 }