Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9208
-gerrit
commit 6ea136ea860140cd2ddd486721431afb24990bac Author: Kenji Chen kenji.chen@intel.com Date: Wed Sep 24 01:18:26 2014 +0800
Broadwell: Synchronization with FRC.
Configure IOSF Port and Grant Count.
Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreoot image and run on Samus to confirm the setting Original-is properly applied. Original-Signed-off-by: Kenji Chen kenji.chen@intel.com Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org
Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 --- src/soc/intel/broadwell/pcie.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f63f6d5..de23f3e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -99,6 +99,27 @@ static void root_port_config_update_gbe_port(void) } }
+static void pcie_iosf_port_grant_count(device_t dev) +{ + u8 update_val; + u32 rpcd = (pci_read_config32(dev, 0xfc) > 14) & 0x3; + + switch (rpcd) { + case 1: + case 3: + update_val = 0x02; + break; + case 2: + update_val = 0x22; + break; + default: + update_val = 0x00; + break; + } + + RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val; +} + static void root_port_init_config(device_t dev) { int rp; @@ -108,7 +129,10 @@ static void root_port_init_config(device_t dev) rpc.new_rpfn = rpc.orig_rpfn; rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; - pcie_update_cfg8(dev, 0xf5, 0xa, 0x5); + /* RP0 f5[3:0] = 0101b*/ + pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + + pcie_iosf_port_grant_count(dev);
rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port();