[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail/cpu.c: Align with Braswell

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43197 )

Change subject: soc/intel/baytrail/cpu.c: Align with Braswell
......................................................................

soc/intel/baytrail/cpu.c: Align with Braswell

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons 
---
M src/soc/intel/baytrail/cpu.c
1 file changed, 3 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/43197/1

diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 6312cdb..9979122 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -13,14 +13,13 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
-
 #include <soc/iosf.h>
 #include <soc/msr.h>
 #include <soc/pattrs.h>
 #include <soc/ramstage.h>

/* Core level MSRs */
-const struct reg_script core_msr_script[] = {
+static const struct reg_script core_msr_script[] = {
    /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
    REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
    REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
@@ -31,7 +30,7 @@
    REG_SCRIPT_END
 };

-static void baytrail_core_init(struct device *cpu)
+static void soc_core_init(struct device *cpu)
 {
    printk(BIOS_DEBUG, "Init BayTrail core.\n");

@@ -54,7 +53,7 @@
 }

static struct device_operations cpu_dev_ops = {
-	.init = baytrail_core_init,
+	.init = soc_core_init,
 };

static const struct cpu_device_id cpu_table[] = {