Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26942
Change subject: {arch,commonlib,cpu,device,drivers,lib,nb,sb}: Use "foo *bar" instead of "foo* bar" ......................................................................
{arch,commonlib,cpu,device,drivers,lib,nb,sb}: Use "foo *bar" instead of "foo* bar"
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/riscv/include/mcall.h M src/arch/riscv/trap_handler.c M src/arch/x86/cpu.c M src/commonlib/lz4.c.inc M src/commonlib/storage/mmc.c M src/commonlib/storage/storage.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/pi/romstage.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/update_ucode.c M src/device/device.c M src/device/oprom/include/x86emu/regs.h M src/device/oprom/yabel/compat/of.h M src/device/oprom/yabel/debug.c M src/device/oprom/yabel/debug.h M src/device/oprom/yabel/vbe.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/state_machine.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/i2c/tpm/tpm.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/drivers/intel/fsp1_0/hob.c M src/drivers/intel/gma/edid.c M src/drivers/pc80/tpm/tis.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/gadget.c M src/drivers/xgi/common/xgi_coreboot.c M src/lib/rtc.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdht/ht_wrapper.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/amd/pi/agesawrapper_call.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/via/vx900/lpc.c M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/cimx/sb800/Amd.h M src/southbridge/amd/cimx/sb800/AmdSbLib.h M src/southbridge/amd/cimx/sb800/amd_pci_int_types.h M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/Amd.h M src/southbridge/amd/cimx/sb900/AmdSbLib.h M src/southbridge/amd/cimx/sb900/amd_pci_int_types.h M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/common/amd_pci_util.h M src/southbridge/amd/pi/hudson/amd_pci_int_types.h M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sr5650/sr5650.c 55 files changed, 101 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/26942/1
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index e4bc36f..56f2821 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -52,11 +52,11 @@ #define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + (void *)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
// hart-local storage, at top of stack #define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) +#define OTHER_HLS(id) ((hls_t*)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))
#define MACHINE_STACK_SIZE RISCV_PGSIZE
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 7b35c2e..1838a2b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -74,8 +74,8 @@ previous_mode, mprv? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); - printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); + printk(BIOS_DEBUG, "Stored ra: %p\n", (void *) tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void *) tf->gpr[2]); }
static void gettimer(void) @@ -201,7 +201,7 @@ printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); if (memWidth == 3) { // load double, handle the issue - void* badAddress = (void*) tf->badvaddr; + void * badAddress = (void *) tf->badvaddr; uint64_t value = 0; for (int i = 0; i < 8; i++) { value <<= 8; @@ -229,7 +229,7 @@ printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); if (memWidth == 3) { // store double, handle the issue - void* badAddress = (void*) tf->badvaddr; + void * badAddress = (void *) tf->badvaddr; uint64_t value = tf->gpr[srcRegister]; for (int i = 0; i < 8; i++) { mprv_write_u8(badAddress+i, value); diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 7a7c99b..6bbeb59 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -116,7 +116,7 @@ { X86_VENDOR_SIS, "SiS SiS SiS ", }, };
-static const char * const x86_vendor_name[] = { +static const char *const x86_vendor_name[] = { [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", [X86_VENDOR_AMD] = "AMD", diff --git a/src/commonlib/lz4.c.inc b/src/commonlib/lz4.c.inc index b3be4e5..f25547d 100644 --- a/src/commonlib/lz4.c.inc +++ b/src/commonlib/lz4.c.inc @@ -38,14 +38,14 @@ **************************************/
/* customized variant of memcpy, which can overwrite up to 7 bytes beyond dstEnd */ -static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) +static void LZ4_wildCopy(void * dstPtr, const void * srcPtr, void * dstEnd) { BYTE* d = (BYTE*)dstPtr; const BYTE* s = (const BYTE*)srcPtr; BYTE* const e = (BYTE*)dstEnd;
#if 0 - const size_t l2 = 8 - (((size_t)d) & (sizeof(void*)-1)); + const size_t l2 = 8 - (((size_t)d) & (sizeof(void *)-1)); LZ4_copy8(d,s); if (d>e-9) return; d+=l2; s+=l2; #endif /* join to align */ diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index d88e469..e09d826 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -529,7 +529,7 @@ const char *mmc_partition_name(struct storage_media *media, unsigned int partition_number) { - static const char * const partition_name[8] = { + static const char *const partition_name[8] = { "User", /* 0 */ "Boot 1", /* 1 */ "Boot 2", /* 2 */ diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index d2b566f..927e12f 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -31,7 +31,7 @@ #define HEX_CAPACITY_MULTIPLIER 1024ULL
struct capacity { - const char * const units; + const char *const units; uint64_t bytes; };
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0ecd040..bf9508a 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -377,8 +377,8 @@ uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); - if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) + void * lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + if (((void *)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", sysinfo, sysinfo + 1, lower_stack_region_boundary); @@ -825,7 +825,7 @@ * * Returns the offset of the link register. */ -static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) +static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) { u32 reg; u32 val; diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index 9a5fbac..f4066e7 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -45,7 +45,7 @@ stack_top += HIGH_ROMSTAGE_STACK_SIZE;
printk(BIOS_DEBUG, "Move CAR stack.\n"); - return (void*)stack_top; + return (void *)stack_top; }
void asmlinkage romstage_after_car(void) diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 9b93870..5583c46 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -42,7 +42,7 @@ } #endif
-static const char * const turbo_state_desc[] = { +static const char *const turbo_state_desc[] = { [TURBO_UNKNOWN] = "unknown", [TURBO_UNAVAILABLE] = "unavailable", [TURBO_DISABLED] = "available but hidden", diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 9ff66e7..7c631a6 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -61,7 +61,7 @@ * Two's complement done over the entire file, including the header */ int i; u32 check = 0; - u32 *raw = (void*) ucode; + u32 *raw = (void *) ucode; for (i = 0; i < ((ucode->total_size) >> 2); i++) { check += raw[i]; } diff --git a/src/device/device.c b/src/device/device.c index 79dceaa..7ba9d0a 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -195,7 +195,7 @@ return val; }
-static const char * resource2str(struct resource *res) +static const char *resource2str(struct resource *res) { if (res->flags & IORESOURCE_IO) return "io"; diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 8eec112..e0908c1 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -306,7 +306,7 @@ unsigned long mem_base; unsigned long mem_size; unsigned long abseg; - void* private; + void * private; X86EMU_regs x86; } X86EMU_sysEnv;
diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h index 31c9b59..8224c78 100644 --- a/src/device/oprom/yabel/compat/of.h +++ b/src/device/oprom/yabel/compat/of.h @@ -35,7 +35,7 @@ #ifndef OF_H #define OF_H #define p32 int -#define p32cast (int) (unsigned long) (void*) +#define p32cast (int) (unsigned long) (void *)
#define phandle_t p32 #define ihandle_t p32 @@ -59,8 +59,8 @@
ihandle_t of_open (const char *); void of_close(ihandle_t); -int of_read (ihandle_t , void*, int); -int of_write (ihandle_t, void*, int); +int of_read (ihandle_t , void *, int); +int of_write (ihandle_t, void *, int); int of_seek (ihandle_t, int, int);
void * of_claim(void *, unsigned int , unsigned int ); diff --git a/src/device/oprom/yabel/debug.c b/src/device/oprom/yabel/debug.c index daa263e..fc226fe 100644 --- a/src/device/oprom/yabel/debug.c +++ b/src/device/oprom/yabel/debug.c @@ -37,7 +37,7 @@ u32 debug_flags = 0;
void -dump(u8 * addr, u32 len) +dump(u8 *addr, u32 len) { printf("\n%s(%p, %x):\n", __func__, addr, len); while (len) { diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index b1a8600..20db261 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -130,6 +130,6 @@
#endif //DEBUG
-void dump(u8 * addr, u32 len); +void dump(u8 *addr, u32 len);
#endif diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 5402ddf..c8b99d5 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -321,7 +321,7 @@ }
static u8 -vbe_get_color(u16 color_number, u32 * color_value) +vbe_get_color(u16 color_number, u32 *color_value) { vbe_prepare(); // call VBE function 09h (Set/Get Palette Data Function) diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 1ca6e5b..ad193e1 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -161,5 +161,5 @@ if (!size) return NULL;
- return (void*)(pos + sizeof(UINT32)); + return (void *)(pos + sizeof(UINT32)); } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index b73c124..673bf9b 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -53,7 +53,7 @@
image = LibAmdLocateImage(agesa, agesa + file_size, 4096, ModuleIdentifier); - StdHeader->ImageBasePtr = (void*) image; + StdHeader->ImageBasePtr = (void *) image; #endif }
@@ -66,10 +66,10 @@ if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)) { agesa_locate_image(&cb->StdHeader); AMD_IMAGE_HEADER *image = - (void*)(uintptr_t)cb->StdHeader.ImageBasePtr; + (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; ASSERT(image); AMD_MODULE_HEADER *module = - (void*)(uintptr_t)image->ModuleInfoOffset; + (void *)(uintptr_t)image->ModuleInfoOffset; ASSERT(module && module->ModuleDispatcher); } } @@ -83,8 +83,8 @@ dispatcher = AmdAgesaDispatcher; #endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) - AMD_IMAGE_HEADER *image = (void*)(uintptr_t)StdHeader->ImageBasePtr; - AMD_MODULE_HEADER *module = (void*)(uintptr_t)image->ModuleInfoOffset; + AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr; + AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset; dispatcher = module->ModuleDispatcher; #endif
diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index 5a208e6..544e8e8 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -73,7 +73,7 @@ };
static inline void *kzalloc(size_t size, int flags) { - void* ptr = malloc(size); + void * ptr = malloc(size); memset(ptr, 0, size); return ptr; } diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 7d69861..447fc24 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -65,7 +65,7 @@ UNKNOWN, };
-static const char * const chip_name[] = { +static const char *const chip_name[] = { [SLB9635] = "slb9635tt", [SLB9645] = "slb9645tt", [UNKNOWN] = "unknown/fallback to slb9635", diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 5a6321d..8880fbd 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -75,7 +75,7 @@ UPD_DATA_REGION fsp_upd_data; #endif
- memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); + memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; FspInitParams.NvsBufferPtr = NULL;
@@ -100,7 +100,7 @@ } #endif /* __PRE_RAM__ */
-volatile u8 * find_fsp () +volatile u8 *find_fsp () {
#ifdef __PRE_RAM__ @@ -221,7 +221,7 @@ }
if (FspHobListPtr == NULL) { - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); + FspHobListPtr = (void *)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); }
printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr); @@ -294,7 +294,7 @@ static void find_fsp_hob_update_mrc(void *unused) { /* Set the global HOB list pointer */ - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); + FspHobListPtr = (void *)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
if (!FspHobListPtr){ printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n"); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index a3a7dd3..b53ece0 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -25,7 +25,7 @@ void * find_and_set_fastboot_cache(void); #endif
-volatile u8 * find_fsp(void); +volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); void FspNotify(u32 Phase); void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr); @@ -42,7 +42,7 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); void print_hob_resource_attributes(void *Hobptr); void print_guid_type_attributes(void *Hobptr); -const char * get_hob_type_string(void *Hobptr); +const char *get_hob_type_string(void *Hobptr); void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); void printguid(EFI_GUID *guid); diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c index 4aac147..83d5543 100644 --- a/src/drivers/intel/fsp1_0/hob.c +++ b/src/drivers/intel/fsp1_0/hob.c @@ -42,7 +42,7 @@ EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType; u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress; u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength; - const char * Hobmemtypenames[15]; + const char *Hobmemtypenames[15];
Hobmemtypenames[0] = "EfiReservedMemoryType"; Hobmemtypenames[1] = "EfiLoaderCode"; @@ -104,7 +104,7 @@ (unsigned long)Hobresaddr, (unsigned long)Hobreslength); }
-const char * get_hob_type_string(void *Hobptr) +const char *get_hob_type_string(void *Hobptr) { EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr; u16 Hobtype = HobHeaderPtr->HobType; diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 316e869..13b301f 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -39,7 +39,7 @@ } }
-static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) +static void intel_gmbus_stop_bus(u8 *mmio, u8 bus) { wait_rdy(mmio); write32(GMBUS0_ADDR, bus); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 3549173..bd1033d 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -109,12 +109,12 @@ */ struct device_name { u16 dev_id; - const char * const dev_name; + const char *const dev_name; };
struct vendor_name { u16 vendor_id; - const char * vendor_name; + const char *vendor_name; const struct device_name* dev_names; };
@@ -443,7 +443,7 @@ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does * not accept the entire command). */ -static u32 tis_senddata(const u8 * const data, u32 len) +static u32 tis_senddata(const u8 *const data, u32 len) { u32 offset = 0; u16 burst = 0; diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index fcc5223..52b4bdd 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -631,7 +631,7 @@
diff = (unsigned)dbg_info->ehci_base - ehci_base; dbg_info->ehci_debug -= diff; - dbg_info->ehci_base = (void*)ehci_base; + dbg_info->ehci_base = (void *)ehci_base;
for (i=0; i<DBGP_MAX_ENDPOINTS; i++) if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID) diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 37e97a3..3254a8a 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -29,7 +29,7 @@ #define USB_HUB_C_PORT_RESET 20
-static int hub_port_status(const char * buf, int feature) +static int hub_port_status(const char *buf, int feature) { return !!(buf[feature>>3] & (1<<(feature&0x7))); } diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 9cd634c..cee7dfb 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -130,8 +130,8 @@
hw_info->ulVideoMemorySize = xgifb_info->video_size;
- xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void*)(intptr_t)xgifb_info->video_base; - xgifb_info->mmio_vbase = (void*)(intptr_t)xgifb_info->mmio_base; + xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void *)(intptr_t)xgifb_info->video_base; + xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base;
dev_info(&pdev->dev, "Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n", diff --git a/src/lib/rtc.c b/src/lib/rtc.c index bd98590..c5c157f 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -31,7 +31,7 @@ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
-static const char * const weekdays[] = { +static const char *const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", };
diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h index 58673aa..ca14816 100644 --- a/src/northbridge/amd/amdht/h3gtopo.h +++ b/src/northbridge/amd/amdht/h3gtopo.h @@ -324,7 +324,7 @@ 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7 };
-static const u8 * const amd_topo_list[] = { +static const u8 *const amd_topo_list[] = { amdHtTopologySingleNode, amdHtTopologyDualNode, amdHtTopologyThreeLine, diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index f4e8337..5e33325 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -55,7 +55,7 @@ *---------------------------------------------------------------------------- */
-static const char * event_class_string_decodes[] = { +static const char *event_class_string_decodes[] = { [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", [HT_EVENT_CLASS_ERROR] = "ERROR", [HT_EVENT_CLASS_HW_FAULT] = "HARDWARE FAULT", @@ -65,7 +65,7 @@
typedef struct { uint32_t code; - const char * string; + const char *string; } event_string_decode_t;
static const event_string_decode_t event_string_decodes[] = { @@ -90,7 +90,7 @@ { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" } };
-static const char * event_string_decode(uint32_t event) { +static const char *event_string_decode(uint32_t event) { uint32_t i; for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++) if (event_string_decodes[i].code == event) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index a66917b..c8578f6 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -289,7 +289,7 @@
const void *agesawrapper_locate_module (const CHAR8 name[8]) { - const void* agesa; + const void * agesa; const AMD_IMAGE_HEADER* image; const AMD_MODULE_HEADER* module; size_t file_size; diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h index 1ed4a4c..bfcd78d 100644 --- a/src/northbridge/amd/pi/agesawrapper_call.h +++ b/src/northbridge/amd/pi/agesawrapper_call.h @@ -30,7 +30,7 @@ * 0x6 = AGESA_CRITICAL * 0x7 = AGESA_FATAL */ -static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +static const char *decodeAGESA_STATUS(AGESA_STATUS sret) { const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", "AGESA_BOUNDS_CHK", "AGESA_ALERT", diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ed79f45..999d5a8 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -43,7 +43,7 @@ + FspInfo->ImageBase); UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32) (VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); + memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); }
typedef struct northbridge_intel_fsp_rangeley_config config_t; diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index 888da8e..eb31655 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -33,7 +33,7 @@ UPD_DATA_REGION *UpdDataRgnPtr; VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); + memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); }
static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) @@ -70,7 +70,7 @@ UPD_DATA_REGION *fsp_upd_data = pFspRtBuffer->Common.UpdDataRgnPtr; #else MEM_CONFIG MemoryConfig; - memset((void*)&MemoryConfig, 0, sizeof(MEM_CONFIG)); + memset((void *)&MemoryConfig, 0, sizeof(MEM_CONFIG)); #endif FspInitParams->NvsBufferPtr = NULL;
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 77aba94..0a4a017 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -54,7 +54,7 @@ u8 cmd = pci_read_config8(igd, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(igd, PCI_COMMAND, cmd); - void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0); + void * bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
/* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 6a27b57..f68031b 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1787,7 +1787,7 @@ csr.csr.buffer_read_ptr)); }
-static void send_heci_packet(struct mei_header *head, u32 * payload) +static void send_heci_packet(struct mei_header *head, u32 *payload) { int len = (head->length + 3) / 4; int i; @@ -1804,7 +1804,7 @@ }
static void -send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress) +send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) { struct mei_header head; int maxlen; @@ -1831,8 +1831,8 @@
/* FIXME: Add timeout. */ static int -recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet, - u32 * packet_size) +recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet, + u32 *packet_size) { union { struct mei_csr csr; @@ -1878,7 +1878,7 @@
/* FIXME: Add timeout. */ static int -recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size) +recv_heci_message(struct raminfo *info, u32 *message, u32 *message_size) { struct mei_header head; int current_position; @@ -2292,9 +2292,9 @@ }
static void -do_fsm(enum state *state, u16 * counter, +do_fsm(enum state *state, u16 *counter, u8 fail_mask, int margin, int uplimit, - u8 * res_low, u8 * res_high, u8 val) + u8 *res_low, u8 *res_high, u8 val) { int lane;
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index f31f032..66f0a10 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1845,7 +1845,7 @@ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; hpet_udelay(1); barrier(); - strobedata = read32((void*)strobeaddr); + strobedata = read32((void *)strobeaddr); barrier(); hpet_udelay(1);
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 075a872..b90e2d4 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -246,7 +246,7 @@ };
#if IS_ENABLED(CONFIG_PIRQ_ROUTE) -void pirq_assign_irqs(const u8 * pirq) +void pirq_assign_irqs(const u8 *pirq) { struct device *lpc;
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 7b74561..328818c 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -17,7 +17,7 @@ #define AMD_PCI_INT_TYPES_H
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -const char * intr_types[] = { +const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", @@ -27,7 +27,7 @@ [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" }; #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -const char * intr_types[] = { +const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 42e2b3a..879b95c 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -61,9 +61,9 @@ #define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) #define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void * ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void * ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void * ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index c13eda4..6210c50 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -28,7 +28,7 @@ #define NUM_IMAGE_LOCATION 32
//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); +typedef void (*CIM_IMAGE_ENTRY) (void * pConfig);
//Hook Call
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h index 854f9c3..300969d 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-const char * intr_types[] = { +const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ebc6ba1..9cc48f9 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -43,14 +43,14 @@ /** * @brief Entry point of Southbridge CIMx callout * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void * pConfig) * * @param[in] func Southbridge CIMx Function ID. * @param[in] data Southbridge Input Data. * @param[in] config Southbridge configuration structure pointer. * */ -static u32 sb800_callout_entry(u32 func, u32 data, void* config) +static u32 sb800_callout_entry(u32 func, u32 data, void * config) { u32 ret = 0; printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h index ec81400..c92ebac 100644 --- a/src/southbridge/amd/cimx/sb900/Amd.h +++ b/src/southbridge/amd/cimx/sb900/Amd.h @@ -61,9 +61,9 @@ #define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) #define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); -typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); -typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void * ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void * ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void * ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h index c13eda4..6210c50 100644 --- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h @@ -28,7 +28,7 @@ #define NUM_IMAGE_LOCATION 32
//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); +typedef void (*CIM_IMAGE_ENTRY) (void * pConfig);
//Hook Call
diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h index 854f9c3..300969d 100644 --- a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h +++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-const char * intr_types[] = { +const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index e792fe3..7b35543 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -38,14 +38,14 @@ /** * @brief Entry point of Southbridge CIMx callout * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void * pConfig) * * @param[in] func Southbridge CIMx Function ID. * @param[in] data Southbridge Input Data. * @param[in] config Southbridge configuration structure pointer. * */ -u32 sb900_callout_entry(u32 func, u32 data, void* config) +u32 sb900_callout_entry(u32 func, u32 data, void * config) { u32 ret = 0;
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 2acd151..ca76809 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -26,8 +26,8 @@
const struct pirq_struct * pirq_data_ptr = NULL; u32 pirq_data_size = 0; -const u8 * intr_data_ptr = NULL; -const u8 * picr_data_ptr = NULL; +const u8 *intr_data_ptr = NULL; +const u8 *picr_data_ptr = NULL;
/* * Read the FCH PCI_INTR registers 0xC00/0xC01 at a diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 452db65..9a4695e 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -32,8 +32,8 @@
extern const struct pirq_struct * pirq_data_ptr; extern u32 pirq_data_size; -extern const u8 * intr_data_ptr; -extern const u8 * picr_data_ptr; +extern const u8 *intr_data_ptr; +extern const u8 *picr_data_ptr;
u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index f898907..8061bf7 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -16,7 +16,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
-const char * intr_types[] = { +const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t", diff --git a/src/southbridge/amd/pi/hudson/gpio.c b/src/southbridge/amd/pi/hudson/gpio.c index 5b2eb4c..d3e5cfa 100644 --- a/src/southbridge/amd/pi/hudson/gpio.c +++ b/src/southbridge/amd/pi/hudson/gpio.c @@ -22,7 +22,7 @@ { uint32_t reg;
- reg = read32((void*)(uintptr_t)gpio_num); + reg = read32((void *)(uintptr_t)gpio_num);
return !!(reg & GPIO_PIN_STS); } diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index cfcddb2..9497934 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -311,9 +311,9 @@
static void internal_gfx_pci_dev_init(struct device *dev) { - unsigned char * bpointer; - volatile u32 * GpuF0MMReg; - volatile u32 * pointer; + unsigned char *bpointer; + volatile u32 *GpuF0MMReg; + volatile u32 *pointer; int i; u16 command; u32 value; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index ef40ffd..457cdf3 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -187,7 +187,7 @@ { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24, romstrap2; - volatile u32 * strap; + volatile u32 *strap;
/* Choose a base address that is unused and routed to the RS780. */ MMIOBase = 0xFFB00000; diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1962ea3..8eb4bc6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -336,7 +336,7 @@ return; }
- mmio_base = (void*)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000); + mmio_base = (void *)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000);
// if (get_nb_rev(nb_dev) == REV_SR5650_A11) { // dword = pci_read_config32(iommu_dev, 0x6c); @@ -352,11 +352,11 @@ dword |= 0x1; pci_write_config32(iommu_dev, 0x44, dword);
- write32((void*)(mmio_base + 0x8), 0x0); - write32((void*)(mmio_base + 0xc), 0x08000000); - write32((void*)(mmio_base + 0x10), 0x0); - write32((void*)(mmio_base + 0x2008), 0x0); - write32((void*)(mmio_base + 0x2010), 0x0); + write32((void *)(mmio_base + 0x8), 0x0); + write32((void *)(mmio_base + 0xc), 0x08000000); + write32((void *)(mmio_base + 0x10), 0x0); + write32((void *)(mmio_base + 0x2008), 0x0); + write32((void *)(mmio_base + 0x2010), 0x0);
/* IOMMU L1 initialization */ for (l1_target = 0; l1_target < 6; l1_target++) {