Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42362 )
Change subject: ACPI: Replace smm_setup_structures() ......................................................................
ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were the same when implemented.
Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/acpi/Kconfig M src/arch/x86/acpi_s3.c M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/smi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/smi.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 34 files changed, 58 insertions(+), 178 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 11ef12a3..07008db 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,6 +24,9 @@ Provide common definitions for Intel hardware PM1_CNT register sleep values.
+config ACPI_NO_SMI_GNVS + bool + config ACPI_NO_PCAT_8259 bool help diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index d4c697e..4872c07 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -4,7 +4,6 @@ #include <string.h> #include <acpi/acpi.h> #include <arch/cpu.h> -#include <cbmem.h> #include <commonlib/helpers.h> #include <cpu/x86/smm.h> #include <fallback.h> @@ -79,16 +78,8 @@
void acpi_resume(void *wake_vec) { - if (CONFIG(HAVE_SMI_HANDLER)) { - void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); - - /* Restore GNVS pointer in SMM if found */ - if (gnvs_address) { - printk(BIOS_DEBUG, "Restore GNVS pointer to %p\n", - gnvs_address); - smm_setup_structures(gnvs_address, NULL, NULL); - } - } + /* Restore GNVS pointer in SMM if found. */ + apm_control(APM_CNT_GNVS_UPDATE);
/* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 3cd387d..499cc5b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,6 +17,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 + select ACPI_NO_SMI_GNVS
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 7bcfa61..533507e 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -17,6 +17,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 + select ACPI_NO_SMI_GNVS
if CPU_AMD_PI
diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index f1031a0..4b63745 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h>
+static void set_smm_gnvs_ptr(void); + int apm_control(u8 cmd) { if (!CONFIG(HAVE_SMI_HANDLER)) @@ -21,7 +24,8 @@ printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); break; case APM_CNT_GNVS_UPDATE: - break; + set_smm_gnvs_ptr(); + return 0; case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "Finalizing SMM.\n"); break; @@ -41,3 +45,32 @@ printk(BIOS_DEBUG, "APMC done.\n"); return 0; } + +static void set_smm_gnvs_ptr(void) +{ + uintptr_t gnvs_address; + + if (CONFIG(ACPI_NO_SMI_GNVS)) { + printk(BIOS_WARNING, "%s() is not implemented\n", __func__); + return; + } + + gnvs_address = (uintptr_t)acpi_get_gnvs(); + if (!gnvs_address) + return; + + /* + * Issue SMI to set the gnvs pointer in SMM. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" (gnvs_address), + "d" (APM_CNT) + ); +} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9db1461..cdc6901 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -48,8 +48,6 @@ void northbridge_smi_handler(void); void southbridge_smi_handler(void);
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2df0b6a..fd2a205 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,6 +56,7 @@ select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select ACPI_NO_SMI_GNVS
config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index ba36e65..125dde6 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -11,11 +11,6 @@ #include <soc/southbridge.h> #include <soc/smi.h>
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47642a9..9bb5604 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ select HAVE_SMI_HANDLER select SSE2 select RTC + select ACPI_NO_SMI_GNVS
config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index a3473aa..fb6d348 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -10,11 +10,6 @@ #include <soc/southbridge.h> #include <soc/smi.h>
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 58238db..c70388a 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -97,22 +97,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index fb63a56..679c04d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -494,7 +494,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 53379a0..1290d62 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -512,7 +512,7 @@ gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT */ acpigen_write_scope("\"); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index e3ebc32..3f3c53f 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -99,22 +99,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b841291..1e96286 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -584,7 +584,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 9d8d25e..317da0c 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -86,22 +86,3 @@ /* Set EOS bit so other SMIs can occur. */ enable_smi(EOS); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 8d75c9a..c497399 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -240,7 +240,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 0b120a7..2fd97da 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -70,22 +70,3 @@ { smm_southbridge_enable(GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 3b3e37a..014625c 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -292,7 +292,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index b4970ad..e7ed28d 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -56,19 +56,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile("outb %%al, %%dx\n\t" - : /* ignore result */ - : "a"(APM_CNT_GNVS_UPDATE), "b"((uint32_t)gnvs), - "d"(APM_CNT)); -} diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6ff836a..414a14f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -655,7 +655,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 6683301..9542562 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -38,6 +38,7 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP + select ACPI_NO_SMI_GNVS select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index abaa453..0261857 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -120,7 +120,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 3da2025..17da9a9 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -968,7 +968,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 6c76825..f54faeb 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -10,11 +10,6 @@
#include "smi.h"
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 6c76825..f54faeb 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -10,11 +10,6 @@
#include "smi.h"
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 038bb37..fb82246 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -665,7 +665,7 @@ #endif
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 913cce0..06d7c74 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -79,25 +79,6 @@ smm_southbridge_enable(PWRBTN_EN | GBL_EN); }
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uintptr_t)gnvs), - "d" (APM_CNT) - ); -} - void smm_southbridge_clear_state(void) { if (smi_enabled()) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 88c5633..55f3a84 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -622,7 +622,7 @@ acpi_create_gnvs(gnvs);
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 27a7c95..db214ee 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -464,7 +464,7 @@ acpi_create_gnvs(gnvs);
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index edd1430..0a2440d 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -623,7 +623,7 @@ acpi_create_gnvs(gnvs);
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4f86e9b..5a6483f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -566,7 +566,7 @@ gnvs->pcnt = dev_count_cpu();
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to SSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6cdbc78..4b12b32 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -721,7 +721,7 @@ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
/* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE);
/* Add it to DSDT. */ acpigen_write_scope("\"); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 48b76e2..6edf5c1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -57,22 +57,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -}