Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39345 )
Change subject: tigerlake: update processor power limits configuration
......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte...
File src/mainboard/google/volteer/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/39345/16/src/mainboard/google/volte...
PS16, Line 55: /* Dynamic Platform Thermal Framework */
: Scope (_SB)
: {
: /* Per board variant specific definitions. */
: #include <variant/acpi/dptf.asl>
: /* Include soc specific DPTF changes */
: #include <soc/intel/common/acpi/dptf.asl>
: /* Include common dptf ASL files */
: #include <soc/intel/common/acpi/dptf/dptf.asl>
: }
This part should go in a separate change to enable DPTF on TGL.
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