21 Dec
2021
21 Dec
'21
6:47 a.m.
Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Simon Yang, Kane Chen, Patrick Rudolph. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )
Change subject: soc/intel/jsl: Add CdClock config ......................................................................
Patch Set 14: Code-Review+2
(1 comment)
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/60009/comment/9e3bad10_485afa55 PS14, Line 209: register "CdClock" = "0xff"
=> Is this the default config in FSP? […]
Ack
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
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