Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41638 )
Change subject: sb/intel/i82371eb: Add #defines for DEVRESx registers ......................................................................
sb/intel/i82371eb: Add #defines for DEVRESx registers
Change [41561] uses DEVRESB.
[41561] https://review.coreboot.org/c/coreboot/+/41561
Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268 Signed-off-by: Keith Hui buurin@gmail.com --- M src/southbridge/intel/i82371eb/i82371eb.h 1 file changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41638/1
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 449161e..f0572ca 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -91,10 +91,20 @@ #define GPO3 0x37
/* Power management (ACPI) PCI registers */ -#define PMBA 0x40 /* Power management base address */ -#define DEFAULT_PMBASE 0xe400 +#define PMBA 0x40 /* Power management base address */ +#define DEFAULT_PMBASE 0xe400 #define PM_IO_BASE DEFAULT_PMBASE -#define PMREGMISC 0x80 /* Miscellaneous power management */ +#define DEVRESA 0X5c /* Device resource A */ +#define DEVRESB 0X60 /* Device resource B */ +#define DEVRESC 0X64 /* Device resource C */ +#define DEVRESD 0x50 /* Device resource D */ +#define DEVRESE 0x68 /* Device resource E */ +#define DEVRESF 0x6c /* Device resource F */ +#define DEVRESG 0x70 /* Device resource G */ +#define DEVRESH 0x74 /* Device resource H */ +#define DEVRESI 0x78 /* Device resource I */ +#define DEVRESJ 0x7c /* Device resource J */ +#define PMREGMISC 0x80 /* Miscellaneous power management */ #define PMIOSE (1 << 0) /* PM I/O Space Enable */
/* Bit definitions */