[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Add memory, romstage and ramstage FSP programming

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Jérémy Compostella, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84443?usp=email )

Change subject: soc/intel/ptl: Add memory, romstage and ramstage FSP programming
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Patch Set 6:

(1 comment)

Patchset:

PS6: 
can we split romstage and ramstage in two different CLs?