[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50147 )

Change subject: soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register
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soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register

Signed-off-by: Felix Held 
Change-Id: Id9838e2433004686e3ea82724c55066bcee1f019
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50147
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Angel Pons 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 72cc60a..8d82035 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -202,10 +202,10 @@
 #define PSP_MAILBOX_OFFSET		0x70 /* offset from BAR3 value */

#define PSP_BAR_ENABLES			0x48
-#define  PSP_MAILBOX_BAR_EN		0x10
+#define  BAR3HIDE			BIT(12) /* Bit to hide BAR3 addr */
+#define  PSP_MAILBOX_BAR_EN		BIT(4)

#define MSR_CU_CBBCFG			0xc00110a2 /* PSP Pvt Blk Base Addr */
-#define   BAR3HIDE			BIT(12) /* Bit to hide BAR3 addr */

typedef struct aoac_devs {
    unsigned int :5;