Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9431
-gerrit
commit a28ddd35c71a0b985f461d27337978a96762b365 Author: Furquan Shaikh furquan@google.com Date: Sat Oct 4 17:01:48 2014 -0700
ryu: Add vboot2 support
CQ-DEPEND=CL:221598, CL:*178568 BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles and boots to kernel prompt
Original-Change-Id: If7c725333b45a92f951ab674c3e4bd6a51c180c2 Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/221577 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org
(cherry picked from commit 9f5a6ae8cb6e7136ab0f0158a864dfc8ccf5c24f) Signed-off-by: Aaron Durbin adurbin@chromium.org
Change-Id: If83dece2b4f2aa7d1457c723131efaa9b1169009 --- src/mainboard/google/rush_ryu/Kconfig | 5 ++- src/mainboard/google/rush_ryu/Makefile.inc | 5 +++ src/mainboard/google/rush_ryu/memlayout.ld | 4 +++ src/mainboard/google/rush_ryu/verstage.c | 53 ++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 6fb21fb..a824f2e 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -76,9 +76,12 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media.
+# For ryu, we are using vboot2. Thus, index for stages: +# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2 +# VBOOT_RAMSTAGE_INDEX -> Use 0x3 config VBOOT_RAMSTAGE_INDEX hex - default 0x2 + default 0x3
config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc index 67a3fac..3b71c79 100644 --- a/src/mainboard/google/rush_ryu/Makefile.inc +++ b/src/mainboard/google/rush_ryu/Makefile.inc @@ -31,6 +31,10 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c
+verstage-y += verstage.c +verstage-y += chromeos.c +verstage-y += reset.c + romstage-y += chromeos.c romstage-y += pmic.c romstage-y += reset.c @@ -45,3 +49,4 @@ ramstage-y += chromeos.c bootblock-y += memlayout.ld romstage-y += memlayout.ld ramstage-y += memlayout.ld +verstage-y += memlayout.ld diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld index 85f4a97..5bd72e5 100644 --- a/src/mainboard/google/rush_ryu/memlayout.ld +++ b/src/mainboard/google/rush_ryu/memlayout.ld @@ -1 +1,5 @@ +#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) +#include <soc/memlayout_vboot2.ld> +#else #include <soc/memlayout_vboot.ld> +#endif diff --git a/src/mainboard/google/rush_ryu/verstage.c b/src/mainboard/google/rush_ryu/verstage.c new file mode 100644 index 0000000..ed83f03 --- /dev/null +++ b/src/mainboard/google/rush_ryu/verstage.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/addressmap.h> +#include <soc/funitcfg.h> +#include <soc/padconfig.h> +#include <soc/verstage.h> +#include <soc/nvidia/tegra/i2c.h> +#include "gpio.h" +#include "pmic.h" + +static const struct pad_config tpm_pads[] = { + PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3), + PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3), +}; + +static const struct pad_config ec_i2c_pads[] = { + PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), + PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), +}; + +static const struct funit_cfg funits[] = { + /* TPM on I2C3 @ 400kHz */ + FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)), + /* EC on I2C2 - pulled to 3.3V @ 100kHz */ + FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)), +}; + +void verstage_mainboard_init(void) +{ + soc_configure_funits(funits, ARRAY_SIZE(funits)); + + /* TPM */ + i2c_init(I2C3_BUS); + /* EC */ + i2c_init(I2C2_BUS); +}