[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Move DEFAULT_MCHBAR to Kconfig

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45619 )

Change subject: nb/intel/x4x: Move DEFAULT_MCHBAR to Kconfig
......................................................................

nb/intel/x4x: Move DEFAULT_MCHBAR to Kconfig

Change-Id: I699e14aee5d1f180ed2586372eae18cf13b76c49
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/iomap.h
M src/northbridge/intel/x4x/x4x.h
5 files changed, 9 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/45619/1

diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 27754c8..b76c78c 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -13,6 +13,10 @@
    select CACHE_MRC_SETTINGS
    select PARALLEL_MP

+config DEFAULT_MCHBAR
+	hex
+	default 0xfed14000
+
 config CBFS_SIZE
    hex
    default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl
index 51deea8..ee30098 100644
--- a/src/northbridge/intel/x4x/acpi/x4x.asl
+++ b/src/northbridge/intel/x4x/acpi/x4x.asl
@@ -12,7 +12,7 @@

Name (PDRS, ResourceTemplate() {
    	Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
-		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
+		Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR,   0x00004000)
    	Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
    	Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
    	Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index d3c3308..4921774 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -16,7 +16,7 @@
 void x4x_early_init(void)
 {
    /* Setup MCHBAR. */
-	pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
+	pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1);

/* Setup DMIBAR. */
    pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h
index 22a675f..03b1b18 100644
--- a/src/northbridge/intel/x4x/iomap.h
+++ b/src/northbridge/intel/x4x/iomap.h
@@ -3,7 +3,6 @@
 #ifndef X4X_IOMAP_H
 #define X4X_IOMAP_H

-#define DEFAULT_MCHBAR		0xfed14000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 #define DEFAULT_HECIBAR		0xfed10000
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 45785a0..95c79e2 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -40,9 +40,9 @@
  * MCHBAR
  */

-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x))))
+#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x))))
+#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x))))
 #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
 #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
 #define MCHBAR8_AND_OR(x, and, or) \