[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68553 )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
......................................................................

mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY

On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.

Before:
Total Time: 1,205,840

After:
Total Time: 995,300

BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.

Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai 
Reviewed-by: V Sowmya 
Reviewed-by: Kangheui Won 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/Kconfig
M src/soc/intel/alderlake/Kconfig
2 files changed, 35 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Kangheui Won: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 577c2ca..7b1b783 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -44,6 +44,7 @@
    select HAVE_SLP_S0_GATE
    select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
    select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_CR50

@@ -58,6 +59,7 @@
    select RT8168_GET_MAC_FROM_VPD
    select RT8168_SET_LED_MODE
    select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
    select TPM_GOOGLE_CR50

config BOARD_GOOGLE_BASEBOARD_NISSA
@@ -81,6 +83,7 @@
    select HAVE_SLP_S0_GATE
    select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
    select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
    select SOC_INTEL_RAPTORLAKE
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_CR50
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1474ce8..08a56c4 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -117,7 +117,6 @@
    select SOC_INTEL_COMMON_RESET
    select SOC_INTEL_CSE_SEND_EOP_EARLY
    select SOC_INTEL_CSE_SET_EOP
-	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY if SOC_INTEL_CSE_LITE_SKU
    select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
    select HAVE_INTEL_COMPLIANCE_TEST_MODE
    select SSE2