[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels

[Subrata Banik (Code Review)]

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Tim Crawford.

Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add function to force disable memory channels
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Patch Set 6:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/2dad38e9_ed6180e0?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> As my previous comment: both Mc0Ch1+Mc0Ch1 enabled or Mc0Ch2+Mc0Ch3 enabled is valid case based on DRAM chip population.

Can you please comment that the configurations below are valid?

1. Mc0Ch0
2. Mc0Ch0+Mc0Ch1
3. Mc0Ch2+Mc0Ch3
4. Mc0Ch2

if  Mc0Ch0+Mc0Ch1 or  Mc0Ch2+Mc0Ch3 are value configuration then Mc0Ch0 or Mc0Ch2 should also be a valid configuration isn't it? vendor can connect single DIMM either ar MC0 channel 0 or 2?