[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Fill SMBIOS type 9

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32294

Change subject: mb/google/sarien: Fill SMBIOS type 9
......................................................................

mb/google/sarien: Fill SMBIOS type 9

Fill mainboard specific system slots information into SMBIOS type 9.

BUG=b:129485789
TEST=Boot up into OS on sarien platform and use dmidecode to confirm
type9 is presnet and valid.

Signed-off-by: Lijian Zhao 
Change-Id: I2e2795fb4573daadc7e84085d21445e43c4699d1
---
M src/mainboard/google/sarien/ramstage.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32294/1

diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 96321f8..a6a4591 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,11 +14,27 @@
  */

#include <arch/acpi.h>
+#include <smbios.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

+static int mainboard_smbios_data(struct device *dev, int *handle,
+				 unsigned long *current)
+{
+	int len = 0;
+	len += smbios_write_type9(
+		current, handle,
+		"NVME SLOT",				/* name */
+		SlotTypeM2Socket2,			/* slot type */
+		SMBIOS_SLOT_3P3V,
+		SMBIOS_SLOT_PME,
+		2, 0);						/* BDF */
+
+	return len;
+}
+
 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
    const struct pad_config *gpio_table;
@@ -31,6 +47,8 @@
 static void mainboard_enable(struct device *dev)
 {
    dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+
+	dev->ops->get_smbios_data = mainboard_smbios_data;
 }

struct chip_operations mainboard_ops = {