Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69227 )
Change subject: soc/intel: Use PCI offset 0x10 over static `Index 0` for PMC ......................................................................
soc/intel: Use PCI offset 0x10 over static `Index 0` for PMC
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10.
TEST=Able to build and boot Google, Rex to OS.
Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Iee2523876a8045e70effd5824afc327d1113038b --- M src/soc/intel/alderlake/pmc.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/elkhartlake/pmc.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/tigerlake/pmc.c 6 files changed, 35 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69227/1
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 87cc54a..d027932 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -85,7 +85,8 @@ struct resource *res;
/* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index f0a32b93..d15e362 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -74,7 +74,8 @@ struct resource *res;
/* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index e556ac8..62f8eb1 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -71,7 +71,8 @@ { struct resource *res;
- mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
res = new_resource(dev, 1); res->base = (resource_t)ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index 4a48345..483cb42 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -71,7 +71,8 @@ { struct resource *res;
- mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
res = new_resource(dev, 1); res->base = (resource_t)ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index 0ab15c4..a031f17 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -80,7 +80,8 @@ struct resource *res;
/* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 31a9cc4..1044bb5 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -84,7 +84,8 @@ struct resource *res;
/* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */ res = new_resource(dev, 1);