[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down

[Jianjun Wang (Code Review)]

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62673 )

Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down
......................................................................

soc/mediatek: Fix null pointer dereference error when PCIe link down

When PCIe link down, dev->chip_info will not be assigned, check its
value to prevent null pointer dereference error when PCIe link down.

TEST=Build pass and no boot error when SSD removed.

Signed-off-by: Jianjun Wang 
Fixes: commit 270b0b60ac (soc/mediatek: Add PCIe support)
Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387
---
M src/soc/mediatek/common/pcie.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/62673/1

diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c
index c05db8c..dc51c86 100644
--- a/src/soc/mediatek/common/pcie.c
+++ b/src/soc/mediatek/common/pcie.c
@@ -212,6 +212,9 @@
 {
    struct mtk_pcie_controller *ctrl = dev->chip_info;

+	if (!ctrl)
+		return;
+
    mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0),
    			ctrl->mmio_res_io);

@@ -224,6 +227,9 @@
    struct mtk_pcie_controller *ctrl = dev->chip_info;
    uintptr_t table;

+	if (!ctrl)
+		return;
+
    /* Initialize I/O space constraints. */
    table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG;
    if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0)