[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add UPDs for support edp power sequence adjust

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to review the following change.

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 2e6f8d4..8921d4e 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -244,6 +244,17 @@
    	uint8_t   boostadj;
    	uint16_t  margin_deemph;
    } edp_tuningset;
+
+	/* edp panel power sequence control*/
+	uint8_t edp_pwr_adjust_enable;
+	uint8_t pwron_digon_to_De;
+	uint8_t pwron_de_to_varybl;
+	uint8_t pwrdown_varybloff_to_de;
+	uint8_t pwrdown_de_to_digoff;
+	uint8_t pwroff_delay;
+	uint8_t pwron_varybl_to_blon;
+	uint8_t pwrdown_bloff_to_varybloff;
+	uint8_t min_allowed_bl_level;
 };

#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 86b3eba..3a1a579 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -155,6 +155,17 @@
    	scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
    	scfg->BoostAdj = cfg->edp_tuningset.boostadj;
    }
+	if (cfg->edp_pwr_adjust_enable) {
+		scfg->pwron_digon_to_De = cfg->pwron_digon_to_De;
+		scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl;
+		scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de;
+		scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff;
+		scfg->pwroff_delay = cfg-> pwroff_delay;
+		scfg->pwron_varybl_to_blon =	cfg-> pwron_varybl_to_blon;
+		scfg->pwrdown_bloff_to_varybloff = cfg-> pwrdown_bloff_to_varybloff;
+		scfg->min_allowed_bl_level = cfg-> min_allowed_bl_level;
+	}
+
 }

void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)