Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.
Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74366 )
Change subject: mb/google/rex/var/rex0: Correct _PLD values for USB C0 ......................................................................
mb/google/rex/var/rex0: Correct _PLD values for USB C0
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+
BUG=b:216490477 TEST=emerg-rex coreboot
Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/74366/1
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 282c3da..3755227 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -153,7 +153,7 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi @@ -194,7 +194,7 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi