Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48632
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Fix PCI routing table ......................................................................
soc/amd/picasso: Fix PCI routing table
The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard.
BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e --- M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/pci_int.asl M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 153 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48632/2