Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add the ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 38 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/1
diff --git a/src/include/elog.h b/src/include/elog.h index 0574819..6dc0423 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -140,15 +140,27 @@ #define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 #define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 #define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 -#define ELOG_WAKE_SOURCE_PME_SATA 0x17 -#define ELOG_WAKE_SOURCE_PME_CSE 0x18 -#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 -#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a -#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b -#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e -#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x17 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x18 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x19 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x1a +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x1b +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x1c +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x1d +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x1e +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x22 +#define ELOG_WAKE_SOURCE_PME_SATA 0x23 +#define ELOG_WAKE_SOURCE_PME_CSE 0x24 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x25 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x26 +#define ELOG_WAKE_SOURCE_PME_XHCI 0x27 +#define ELOG_WAKE_SOURCE_PME_XDCI 0x28 +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x29 +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x2a +#define ELOG_WAKE_SOURCE_PME_WIFI 0x2b
struct elog_event_data_wake { u8 source; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..355e8ce 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -121,13 +121,14 @@ #define RP_PME_STS_BIT (1 << 16) static void pch_log_rp_wake_source(void) { - size_t i; + uint8_t i; #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else struct device *dev; #endif uint32_t val; + uint8_t maxports;
struct pme_status_info pme_status_info[] = { { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, @@ -142,9 +143,23 @@ { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, };
- for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + maxports = min(CONFIG(MAX_ROOT_PORTS), ARRAY_SIZE(pme_status_info)); + + for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev;
if (!dev)