[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59566 )

Change subject: soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12
......................................................................

soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12

To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366.

TEST=build pass
BUG=b:202871018

Signed-off-by: James Lo 
Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/soc/mediatek/mt8186/include/soc/mt6366.h
M src/soc/mediatek/mt8186/mt6366.c
2 files changed, 62 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h
index 76fcf54..af77da2 100644
--- a/src/soc/mediatek/mt8186/include/soc/mt6366.h
+++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h
@@ -28,6 +28,9 @@
    PMIC_TOP_TMA_KEY		= 0x03a8,
    PMIC_PWRHOLD			= 0x0a08,
    PMIC_CPSDSA4			= 0x0a2e,
+	PMIC_VPROC12_OP_EN		= 0x1410,
+	PMIC_VPROC12_DBG0		= 0x141e,
+	PMIC_VPROC12_VOSEL		= 0x1426,
    PMIC_VCORE_OP_EN		= 0x1490,
    PMIC_VCORE_DBG0			= 0x149e,
    PMIC_VCORE_VOSEL		= 0x14aa,
@@ -37,6 +40,9 @@
    PMIC_VDRAM1_VOSEL		= 0x1626,
    PMIC_SMPS_ANA_CON0		= 0x1808,
    PMIC_VDDQ_OP_EN			= 0x1b16,
+	PMIC_VSRAM_PROC12_OP_EN		= 0x1b90,
+	PMIC_VSRAM_PROC12_DBG0		= 0x1ba2,
+	PMIC_VSRAM_PROC12_VOSEL		= 0x1bf0,
    PMIC_LDO_VMC_CON0		= 0x1cc4,
    PMIC_LDO_VMC_OP_EN		= 0x1cc6,
    PMIC_LDO_VMCH_CON0		= 0x1cd8,
@@ -53,6 +59,8 @@
    MT6366_VDDQ,
    MT6366_VMCH,
    MT6366_VMC,
+	MT6366_VPROC12,
+	MT6366_VSRAM_PROC12,
    MT6366_REGULATOR_NUM,
 };

diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c
index e63a264..406c524 100644
--- a/src/soc/mediatek/mt8186/mt6366.c
+++ b/src/soc/mediatek/mt8186/mt6366.c
@@ -493,6 +493,50 @@
    udelay(1);
 }

+static u32 pmic_get_vproc12_vol(void)
+{
+	u16 vol_reg;
+
+	vol_reg = pwrap_read_field(PMIC_VPROC12_DBG0, 0x7F, 0);
+	return 500000 + vol_reg * 6250;
+}
+
+static void pmic_set_vproc12_vol(u32 v_uv)
+{
+	u16 vol_reg;
+
+	assert(v_uv >= 500000);
+	assert(v_uv <= 1293750);
+
+	vol_reg = (v_uv - 500000) / 6250;
+
+	pwrap_write_field(PMIC_VPROC12_OP_EN, 1, 0x7F, 0);
+	pwrap_write_field(PMIC_VPROC12_VOSEL, vol_reg, 0x7F, 0);
+	udelay(1);
+}
+
+static u32 pmic_get_vsram_proc12_vol(void)
+{
+	u16 vol_reg;
+
+	vol_reg = pwrap_read_field(PMIC_VSRAM_PROC12_DBG0, 0x7F, 0);
+	return 500000 + vol_reg * 6250;
+}
+
+static void pmic_set_vsram_proc12_vol(u32 v_uv)
+{
+	u16 vol_reg;
+
+	assert(v_uv >= 500000);
+	assert(v_uv <= 1293750);
+
+	vol_reg = (v_uv - 500000) / 6250;
+
+	pwrap_write_field(PMIC_VSRAM_PROC12_OP_EN, 1, 0x7F, 0);
+	pwrap_write_field(PMIC_VSRAM_PROC12_VOSEL, vol_reg, 0x7F, 0);
+	udelay(1);
+}
+
 static u32 pmic_get_vdram1_vol(void)
 {
    u32 vol_reg;
@@ -779,6 +823,12 @@
    case MT6366_VMC:
    	pmic_set_vmc_vol(voltage_uv);
    	break;
+	case MT6366_VPROC12:
+		pmic_set_vproc12_vol(voltage_uv);
+		break;
+	case MT6366_VSRAM_PROC12:
+		pmic_set_vsram_proc12_vol(voltage_uv);
+		break;
    default:
    	printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id);
    	break;
@@ -798,6 +848,10 @@
    	return pmic_get_vmch_vol();
    case MT6366_VMC:
    	return pmic_get_vmc_vol();
+	case MT6366_VPROC12:
+		return pmic_get_vproc12_vol();
+	case MT6366_VSRAM_PROC12:
+		return pmic_get_vsram_proc12_vol();
    default:
    	printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id);
    	break;