Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6096
-gerrit
commit c5bce72140b0a7b1e202fc55d53dd37f04942680 Author: Martin Roth martin.roth@se-eng.com Date: Fri Jun 20 20:37:25 2014 -0600
fsp_baytrail: Set FSP TSEG size by the Kconfig choice
- Add Kconfig selections for TSEG size for baytrail. - Remove MrcInitTsegSize variable and #defines from chip.h - Pass the TSEG size in MB to the FSP.
- Remove the MrcInitTsegSize register config from bayleybay_fsp devicetree.cb
Change-Id: I1eb1711fe449f5031e20cb724cd5dd8203aab710 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/mainboard/intel/bayleybay_fsp/devicetree.cb | 1 - src/soc/intel/fsp_baytrail/Kconfig | 41 ++++++++++++++++++++--- src/soc/intel/fsp_baytrail/chip.h | 15 +-------- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 3 +- 4 files changed, 39 insertions(+), 21 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb index cfc71ab..b9e2db4 100644 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb @@ -27,7 +27,6 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 312449e..4da0fcd 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -63,15 +63,48 @@ config CPU_ADDR_BITS int default 36
+choice + prompt "Set TSEG Size" + default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB + default SET_TSEG_2MB if SET_DEFAULT_TSEG_2MB + default SET_TSEG_4MB if SET_DEFAULT_TSEG_4MB + default SET_TSEG_8MB if SET_DEFAULT_TSEG_8MB + +config SET_TSEG_1MB + bool "1 MB" + help + Set the TSEG area to 1 MB. + +config SET_TSEG_2MB + bool "2 MB" + help + Set the TSEG area to 2 MB. + +config SET_TSEG_4MB + bool "4 MB" + help + Set the TSEG area to 4 MB. + +config SET_TSEG_8MB + bool "8 MB" + help + Set the TSEG area to 8 MB. + +endchoice + config SMM_TSEG_SIZE hex - default 0x100000 - help - This is set by the FSP + default 0x200000 if SET_TSEG_2MB + default 0x400000 if SET_TSEG_4MB + default 0x800000 if SET_TSEG_8MB + default 0x100000 # SET_TSEG_1MB
config SMM_RESERVED_SIZE hex - default 0x100000 + default 0x200000 if SET_TSEG_2MB + default 0x400000 if SET_TSEG_4MB + default 0x800000 if SET_TSEG_8MB + default 0x100000 # SET_TSEG_1MB
config VGA_BIOS_ID string diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 7e86862..5e27d9a 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -50,20 +50,6 @@ struct soc_intel_fsp_baytrail_config { #define SATA_MODE_AHCI 0x02
/* - * MrcInitTsegSize - * 0x01, "1 MB" - * 0x02, "2 MB" - * 0x04, "4 MB" - * 0x08, "8 MB" - */ - uint16_t MrcInitTsegSize; - #define TSEG_SIZE_DEFAULT 0 - #define TSEG_SIZE_1_MB 1 - #define TSEG_SIZE_2_MB 2 - #define TSEG_SIZE_4_MB 4 - #define TSEG_SIZE_8_MB 8 - - /* * MrcInitMmioSize * 0x400, "1.0 GB"s * 0x600, "1.5 GB" @@ -76,6 +62,7 @@ struct soc_intel_fsp_baytrail_config { #define MMIO_SIZE_2_0_GB 0x800
/* + * eMMCBootMode * NOTE: These are offset by 1 to set 0 as "use default". This is so that * if the register value is not set in the devicetree.cb file, the default diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 60a1f7a..10f4283 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -102,8 +102,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) UpdData->PcdLpssSioEnablePciMode = config->LpssSioEnablePciMode - LPSS_PCI_MODE_DISABLE;
- if (config->MrcInitTsegSize != TSEG_SIZE_DEFAULT) - UpdData->PcdMrcInitTsegSize = config->MrcInitTsegSize; + UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
if (config->MrcInitMmioSize != MMIO_SIZE_DEFAULT)