Attention is currently required from: Reka Norman, Krishna P Bhat D, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61127 )
Change subject: soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N ......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/alderlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/61127/comment/10bb0267_3ec77fe7 PS2, Line 32: Method(_INI) { : /* Clear register 0x1C20/0x4820 */ : SCSC (PID_EMMC) : }
This was initially added and reviewed in this patch, https://review.coreboot.org/c/coreboot/+/25290. […]
Gotcha, can we add comments to this file then explaining why this is done?
File src/soc/intel/alderlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/61127/comment/40b8fbb1_fb3222fc PS3, Line 37: Method(_PS0, 0, Serialized) { : Stall (50) // Sleep 50 us : : PGEN = 0 // Disable PG : : /* Clear register 0x1C20/0x4820 */ : SCSC (PID_EMMC) : : /* Set Power State to D0 */ : PMCR = PMCR & 0xFFFC : TEMP = PMCR : } : : Method(_PS3, 0, Serialized) { : PGEN = 1 // Enable PG : : /* Set Power State to D3 */ : PMCR = PMCR | 0x0003 : TEMP = PMCR : } Curious why _PS0 and _PS3 methods are required for the eMMC device? Is the kernel driver not capable of configuring these PCI registers?