[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: set default PL4 values for differnt SKUs

[Sumeet R Pawnikar (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56917 )

Change subject: soc/intel/alderlake: set default PL4 values for differnt SKUs
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soc/intel/alderlake: set default PL4 values for differnt SKUs

Set default PL4 values for various alderlake CPU SKUs.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board.

Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/alderlake/chipset.cb
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56917/1

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index 2d5c54e..05da658 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -5,21 +5,25 @@
    register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{
    	.tdp_pl1_override = 15,
    	.tdp_pl2_override = 55,
+		.tdp_pl4 = 123,
    }"

register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{
    	.tdp_pl1_override = 28,
    	.tdp_pl2_override = 64,
+		.tdp_pl4 = 140,
    }"

register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{
    	.tdp_pl1_override = 45,
    	.tdp_pl2_override = 115,
+		.tdp_pl4 = 215,
    }"

register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{
    	.tdp_pl1_override = 9,
    	.tdp_pl2_override = 30,
+		.tdp_pl4 = 68,
    }"

device domain 0 on