[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for ModPhyIfValue

[Mario Scheithauer (Code Review)]

Attention is currently required from: Sean Rhodes.

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75855?usp=email )

Change subject: soc/intel/apollolake: Switch to snake case for ModPhyIfValue
......................................................................

soc/intel/apollolake: Switch to snake case for ModPhyIfValue

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'ModPhyIfValue'.

Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/google/octopus/variants/baseboard/devicetree.cb
M src/mainboard/starlabs/lite/variants/glk/devicetree.cb
M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
5 files changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75855/1

diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index fdfcd61..c6bfe54 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -290,5 +290,5 @@

# FSP UPD to modify the Integrated Filter (IF) value
    # Set it to default value: 0x12
-	register "ModPhyIfValue" = "0x12"
+	register "mod_phy_if_value" = "0x12"
 end
diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
index abfbc0a..2f58a7b 100644
--- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb
@@ -26,7 +26,7 @@

register "pnp_settings"			= "PNP_PERF_POWER"

-	register "ModPhyIfValue"		= "0x12"
+	register "mod_phy_if_value"		= "0x12"

register "prt0_gpio"			= "GPIO_PRT0_UDEF"

diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
index 3102b1f..fe32143c5d 100644
--- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
+++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
@@ -26,7 +26,7 @@

register "pnp_settings"			= "PNP_PERF_POWER"

-	register "ModPhyIfValue"		= "0x12"
+	register "mod_phy_if_value"		= "0x12"

register "prt0_gpio"			= "GPIO_PRT0_UDEF"

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e3bfa1e..a29ba3b 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -612,7 +612,7 @@
    /*
     * Options to change USB3 ModPhy setting for Integrated Filter value.
     */
-	silconfig->ModPhyIfValue = cfg->ModPhyIfValue;
+	silconfig->ModPhyIfValue = cfg->mod_phy_if_value;

/*
     * Options to bump USB3 LDO voltage with 40mv.
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index c1bc020..26e4478 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -190,7 +190,7 @@
     * value. Default is 0 to not changing default IF value (0x12). Set
     * value with the range from 0x01 to 0xff to change IF value.
     */
-	uint8_t ModPhyIfValue;
+	uint8_t mod_phy_if_value;

/* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
     * LDO voltage. Set TRUE to increase LDO voltage with 40mV.