[coreboot-gerrit] [L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard

[Mark Chang (Code Review)]

Attention is currently required from: Angel Pons, Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, [e-mail].

Mark Chang has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email )

Change subject: Add support for MiTAC Computing Whitestone-2 mainboard
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Patch Set 1:

(10 comments)

File configs/config.mitaccomputing_ws_2:

https://review.coreboot.org/c/coreboot/+/85532/comment/cd2aab08_34d6c43d?usp... :
PS1, Line 15: CONFIG_X2APIC_LATE_WORKAROUND=y
> Is this needed for all SPR-SP mainboards?

We only verified Intel 5433N on our Whitestone-2.

File src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl:

https://review.coreboot.org/c/coreboot/+/85532/comment/61dcd260_63f9fb2f?usp... :
PS1, Line 4: #include <soc/intel/common/acpi/acpi_wake_source.asl>
> Not needed for this?

Will remove it.

https://review.coreboot.org/c/coreboot/+/85532/comment/7ec3782a_4900d4dd?usp... :
PS1, Line 13: }
> #include <arch/x86/post. […]

Add "#include <arch/x86/acpi/post.asl> will trigger build error.

https://review.coreboot.org/c/coreboot/+/85532/comment/723f114e_27e9d7de?usp... :
PS1, Line 30:
> I think these methods might be needed for ASL to compile, but I would prefer removing them if possib […]

We will remove it.

File src/mainboard/mitaccomputing/whitestone-2/board_info.txt:

PS1:
> nit: Missing `ROM package`

Update ROM package: SOIC-16

File src/mainboard/mitaccomputing/whitestone-2/bootblock.c:

https://review.coreboot.org/c/coreboot/+/85532/comment/10278896_4fe09c3b?usp... :
PS1, Line 18: static void enable_espi_lpc_io_windows(void)
> I think that library is for ramstage. Also, other Xeon-SP boards do this. […]

We could use below APIs to update it.
- lpc_open_pmio_window(0x2e, 2);
- lpc_open_pmio_window(0x3f8, 8);
- lpc_io_setup_comm_a_b();

https://review.coreboot.org/c/coreboot/+/85532/comment/a71aef7a_0ae18f50?usp... :
PS1, Line 23: 	 * For that end it is wired into BMC virtual port.
> Is SUART2 has s port IO map as SUART1?

The Whitestone-2 only use SUART1.
 - lpc_open_pmio_window(0x2e, 2);
 - lpc_open_pmio_window(0x3f8, 8);
 - lpc_io_setup_comm_a_b();

File src/mainboard/mitaccomputing/whitestone-2/dsdt.asl:

https://review.coreboot.org/c/coreboot/+/85532/comment/f5d32fb3_43aec3a9?usp... :
PS1, Line 10: 	0x20110725	// OEM revision
> The "OEM revision" comment means this number was chosen to match that of vendor firmware (BIOS/UEFI) […]

Remove it

File src/mainboard/mitaccomputing/whitestone-2/mainboard.c:

https://review.coreboot.org/c/coreboot/+/85532/comment/b0d3b80f_f03df174?usp... :
PS1, Line 80: };
> It's invoked automatically

Angel, you're right, it's invoked automatically.

File src/mainboard/mitaccomputing/whitestone-2/romstage.c:

https://review.coreboot.org/c/coreboot/+/85532/comment/40a48d72_77615380?usp... :
PS1, Line 18: Protocl
> typo […]

resolved